NT256D64S88B1G Datasheet, PDF (22/28 Pages) List of Unclassifed Manufacturers – 184 pin Unbuffered DDR DIMM

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK is V_REF.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
high to low at this time, depending on t_DQSS.
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V_{OH (AC)} and V_{OL (AC)}.
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V_{OH (AC)} and V_{OL (AC)}.
11. CK/CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design
or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time. For example, for PC2100 at CL= 2.5, t_DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase t_IS and t_IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
Delta (t_IS)
Delta (t_IH)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+50
0
ps
1, 2
0.3 V/ns
+100
0
ps
1, 2
1. Input slew rate is based on the lesser of the slew rates determined by either V_{IH (AC)} to V_{IL (AC)} or V_{IH (DC)} to V_{IL (DC)}, similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t_DS and t_DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
Delta (t_DS)
Delta (t_DH)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+75
+75
ps
1, 2
0.3 V/ns
+150
+150
ps
1, 2
1. I/O slew rate is based on the lesser of the slew rates determined by either V_{IH (AC)} to V_{IL (AC)} or V_{IH (DC)} to V_{IL (DC)}, similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t_DS and t_DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
0.0 ns/V
Delta (t_DS)
0
Delta (t_DH)
0
Unit
Note
ps
1-4
0.25 ns/V
+50
+50
ps
1-4
0.5 ns/V
+100
+100
ps
1-4
1. Input slew rate is based on the lesser of the slew rates determined by either V_{IH (AC)} to V_{IL (AC)} or V_{IH (DC)} to V_{IL (DC)}, similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t_DS and t_DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 2.2
Aug 3, 2004
Preliminary
22
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