NT256D64S88B1G Datasheet, PDF (10/28 Pages) List of Unclassifed Manufacturers – 184 pin Unbuffered DDR DIMM

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Serial Presence Detect
SPD Description
Byte
0
Description
Number of Serial PD Bytes Written during Production
1
Total Number of Bytes in Serial PD device
2
Fundamental Memory Type
3
Number of Row Addresses on Assembly
4
Number of Column Addresses on Assembly
5
Number of DIMM Rank
6
Data Width of Assembly
7
Data Width of Assembly (cont’)
8
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time
9
CL=2.5
DDR SDRAM Device Access Time from Clock
10
CL=2.5
11
DIMM Configuration Type
12
Refresh Rate/Type
13
Primary DDR SDRAM Width
14
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
15
Access
DDR SDRAM Device Attributes: Burst Length
16
Supported
DDR SDRAM Device Attributes: Number of Device
17
Banks
DDR SDRAM Device Attributes:
18
CAS Latencies Supported
19
DDR SDRAM Device Attributes: CS Latency
20
DDR SDRAM Device Attributes: WE Latency
21
DDR SDRAM Device Attributes:
22
DDR SDRAM Device Attributes: General
Minimum Clock Cycle
23
CL=2.5
Maximum Data Access Time from Clock at
24
CL=2
25
Minimum Clock Cycle Time at CL=1
Byte
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
64-71
72
73-90
91-92
93-94
95-98
99-127
Description
Maximum Data Access Time from Clock at CL=1
Minimum Row Precharge Time (t_RP)
Minimum Row Active to Row Active delay (t_RRD)
Minimum RAS to CAS delay (t_RCD)
Minimum RAS Pulse Width (t_RAS)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
Minimum Active/Auto-refresh Time (t_RC)
Auto-refresh to Active/Auto-refresh Command Period
(t_RFC)
Max Cycle Time (t_{CK max})
Maximum DQS-DQ Skew Time (t_DQSQ)
Maximum Read Data Hold Skew Factor (t_QHS)
Reserved
SPD Revision
Checksum Data
Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Part number
Module Revision Code
Module Manufacturing Data
yy= Binary coded decimal year code, 0-99(Decimal),
00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal),
01-34(Hex)
Module Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
10
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