NT256D64S88B1G Datasheet, PDF (21/28 Pages) List of Unclassifed Manufacturers – 184 pin Unbuffered DDR DIMM

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
T_A = 0 °C ~ 70 °C; V_DDQ= V_DD= 2.5V ± 0.2V (PC2100/PC2700); V_DDQ= V_DD= 2.6V ± 0.1V (PC3200) (Part 2 of 2)
Symbol
Parameter
Address and control input setup time
t_IS
(slow slew rate)
5T
PC3200
Min. Max.
0.7
6K
PC2700
Min. Max.
0.8
75B
PC2100
Min. Max.
1.0
Unit Notes
2-4,
ns 10-12,
14
t_IPW
Input pulse width
2.2
2.2
2.2
ns 2-4, 12
t_{RP RE}
t_{RP ST}
t_RAS
Read preamble
Read postamble
Active to Precharge command
0.9
1.1
0.9
1.1
0.9
1.1
t_CK
1-4
0.40
0.60
0.40
0.60
0.40
0.60
t_CK
1-4
42ns 120us 42ns 120us 45ns 120us
1-4
t_RC
Active to Active/Auto-refresh command period
55
60
65
ns
1-4
Auto-refresh to Active/Auto-refresh command
t_RFC
70
72
75
ns
1-4
period
t_RCD Active to Read or Write delay
15
18
20
ns
1-4
t_RAP Active to Read Command with Auto-precharge
15
18
20
ns
1-4
t_RP
Precharge command period
15
18
20
ns
1-4
t_RRD Active bank A to Active bank B command
10
12
15
ns
1-4
t_WR
Write recovery time
15
(t_WR/
t_DAL
Auto-precharge write recovery + precharge time
t_CK ) +
(t_RP /
t_CK )
t_WTR Internal write to read command delay
1
15
(t_WR/
t_CK ) +
(t_RP /
t_CK )
1
15
(t_WR/
t_CK ) +
(t_RP /
t_CK )
1
ns
1-4
t_CK 1-4, 13
t_CK
1-4
t_PDEX Power down exit time
5
6
7.5
ns
1-4
t_XSNR Exit self-refresh to non-read command
75
75
75
ns
1-4
t_XSRD
t_REFI
Exit self-refresh to read command
Average Periodic Refresh Interval
200
200
200
t_CK
1-4
7.8
7.8
7.8
µs 1-4, 8
REV 2.2
Aug 3, 2004
Preliminary
21
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