NT256D64S88B1G Datasheet, PDF (20/28 Pages) List of Unclassifed Manufacturers – 184 pin Unbuffered DDR DIMM

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
T_A = 0 °C ~ 70 °C; V_DDQ= V_DD= 2.5V ± 0.2V (PC2100/PC2700); V_DDQ= V_DD= 2.6V ± 0.1V (PC3200) (Part 1 of 2)
Symbol
Parameter
t_AC
t_DQSCK
t_CH
t_CL
t_CK
t_CK
t_CK
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time CL=3
Clock cycle time CL=2.5
Clock cycle time CL=2
5T
PC3200
Min. Max.
-0.65 +0.65
-0.55 +0.55
0.45 0.55
0.45 0.55
5
8
6
12
-
-
6K
PC2700
Min. Max.
-0.7
+0.7
-0.7
+0.7
0.45 0.55
0.45 0.55
-
-
6
12
7.5
12
75B
PC2100
Unit Notes
Min. Max.
-0.75 +0.75 ns
1-4
-0.75 +0.75 ns
1-4
0.45
0.55
t_CK
1-4
0.45
0.55
t_CK
1-4
-
-
7.5
12
ns
1-4
10
12
ns
1-4
t_DH
DQ and DM input hold time
1-4,
0.4
0.45
0.5
ns
15, 16
t_DS
DQ and DM input setup time
t_DIPW DQ and DM input pulse width (each input)
0.4
1.75
0.45
1.75
0.5
1.75
1-4,
ns
15, 16
ns
1-4
t_HZ
Data-out high-impedance time from CK/CK
-0.6
+0.6
-0.7
+0.7 -0.75 +0.75 ns 1-4, 5
t_LZ
Data-out low-impedance time from CK/CK
t_DQSQ
t_HP
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle;
defined by clk high (t_CH) or clk low (t_CL) time
t_QH
t_QHS
t_DQSS
t_DQSL,
t_DQSH
t_DSS
t_DSH
t_MRD
Data output hold time from DQS
Data hold Skew Factor
Write command to 1st DQS latching transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle time
t_WPRES Write preamble setup time
t_WPST
t_WPRE
t_IH
t_IS
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
(fast slew rate)
Address and control input hold time
t_IH
(slow slew rate)
-0.6
t_CH or
t_CL
t_HP -
t_QHS
0.75
0.35
0.2
0.2
2
0
0.40
0.25
0.6
0.6
0.7
+0.6
0.4
0.5
1.25
0.60
-0.7
t_CH or
t_CL
t_HP -
t_QHS
0.75
0.35
0.2
0.2
2
0
0.40
0.25
0.75
0.75
0.8
+0.7
0.45
0.55
1.25
0.60
-0.75 +0.75 ns 1-4, 5
0.5
ns
1-4
t_CH or
t_CL
t_CK
1-4
t_HP -
t_QHS
t_CK
1-4
0.75 ns
1-4
0.75
1.25
t_CK
1-4
0.35
t_CK
1-4
0.2
t_CK
1-4
0.2
t_CK
1-4
2
t_CK
1-4
0
ns 1-4, 7
0.40
0.25
0.9
0.9
1.0
0.60
t_CK 1-4, 6
t_CK
1-4
2-4, 9,
ns
11, 12
2-4, 9,
ns
11, 12
2-4,
ns 10, 11,
12, 14
REV 2.2
Aug 3, 2004
Preliminary
20
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