SI5600 Datasheet, PDF (21/28 Pages) List of Unclassifed Manufacturers – SiPHY-TM OC-192/STM-64 SONET/SDH TRANSCEIVER

Si5600
Pin Number(s)
Name
I/O
G4
RESET
I
C6–7, D3, E12,
F4, K4, M10–11,
M8
RSVD_GND
E4, G12
RSVD_VDD33
A2–3
RXCLK1+,
O
RXCLK1–
B2–3
RXCLK2+,
O
RXCLK2–
C12
RXCLK2DIV
I
C8
RXCLK2DSBL
I
D1, E1
RXDIN+,
I
RXDIN–
A4–14, B4–14, RXDOUT[15:0]+, O
C13–14, D13– _{RXDOUT[15:0]–}
14, E13–14,
F13–14, G13,
H13
F3
RXLOL
O
Signal Level
Description
LVTTL
Device Reset.
Forcing this input low for a at least 1 µs will cause
a device reset. For normal operation, this pin
should be held high.
Reserved Tie to Ground.
Must tie directly to GND for proper operation.
LVDS
LVDS
LVTTL
LVTTL
High Speed
Differential
LVDS
LVTTL
Reserved Tie to VDD33.
Must tie directly to VDD33 for proper operation.
Differential Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down by 16 and output on CLK-
OUT. In the absence of data, a stable clock on
RXCLK1 can be maintained by asserting LTR.
Differential Clock Output 2.
An auxiliary output clock is provided on this pin
that may be a divided down version of the high
speed clock recovered from the signal present on
RXDIN. The divide factor used in generating
RXCLK2 is set via RXCLK2DIV.
Clock Divider Select.
This input selects the divide factor used to gener-
ate the RXCLK2 output. When this input is driven
low, RXCLK2 is 1/16th the recovered high speed
clock. When driven high, RXCLK2 is 1/64th the
recovered high speed clock rate.
RXCLK2 Disable.
Driving this input high will disable the RXCLK2
output. This would be used to save power in
applications that do not require an auxiliary clock.
Differential Data Input.
Clock and data are recovered from the high
speed data signal present on these pins.
Differential Parallel Data Output.
The data recovered from the signal present on
RXDIN is demultiplexed and output as a 16-bit
parallel word via RXDOUT[15:0]. These outputs
are updated on the rising edge of RXCLK1.
Loss-of-Lock.
This output is driven low when the recovered
clock frequency deviates from the reference
clock by the amount specified in Table 5.
Preliminary Rev. 0.31
21