SI5600 Datasheet, PDF (14/28 Pages) List of Unclassifed Manufacturers – SiPHY-TM OC-192/STM-64 SONET/SDH TRANSCEIVER

Si5600
traditional analog PLL implementations, the loop filter
bandwidth is controlled by a digital filter inside the
DSPLL and can be changed without any modification to
external components.
DSPLL^™ Clock Multiplier Unit
The Si5600’s clock multiplier unit (CMU) uses Silicon
Laboratories’ proprietary DSPLL technology to generate
a low jitter, high frequency clock source capable of
producing a high speed serial clock and data output with
significant margin to the SONET/SDH specifications.
This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly
found in analog PLL designs. This algorithm processes
the phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscillator (VCO). Because external loop filter
components are not required, sensitive noise entry
points are eliminated, thus making the DSPLL less
susceptible to board-level noise sources. Therefore,
SONET/SDH jitter compliance is easier to attain in the
application.
Programmable Loop Filter Bandwidth
The digitally implemented loop filter allows for two
bandwidth settings that provide either wideband or
narrowband jitter transfer characteristics. The filter
bandwidth is selected via the BWSEL control input. In
traditional PLL implementations, changing the loop filter
bandwidth would require changing the values of
external loop filter components.
In narrowband mode, a loop filter cutoff of 12 kHz is
provided. This setting makes the Si5600 more tolerant
to jitter on the reference clock source. As a result,
distribution circuitry used to generate the physical layer
reference clocks can be simplified without
compromising jitter margin to the SONET/SDH
specification.
In wideband mode, the loop filter provides a cutoff of
50 kHz. This setting is desirable in applications where
the reference clock is provided by a low jitter source like
the Si5364 Clock Synchronization IC or Si5320
Precision Clock Multiplier/Jitter Attenuator IC. This
allows the DSPLL to more closely track the precision
reference source, resulting in the best possible jitter
performance.
Serialization
The Si5600 includes serialization circuitry that
combines a FIFO with a parallel to serial shift register.
Low speed data on the parallel input bus, TXDIN[15:0],
is latched into the FIFO on the rising edge of
TXCLK16IN. The data in the FIFO is clocked into the
shift register by an output clock, TXCLK16OUT, that is
produced by dividing down the high speed transmit
clock, TXCLKOUT, by a factor of 16. The TXCLK16OUT
clock output is provided to support 16-bit word transfers
between the Si5600 and upstream devices using a
counter clocking scheme. The high-speed serial data
stream is clocked out of the shift register using
TXCLKOUT.
Input FIFO
The Si5600 integrates a FIFO to decouple data
transferred into the FIFO via TXCLK16IN from data
transferred into the shift register via TXCLK16OUT. The
FIFO is eight parallel words deep and accommodates
any static phase delay that may be introduced between
TXCLK16OUT and TXCLK16IN in counter clocking
schemes. Furthermore, the FIFO will accommodate a
phase drift or wander between TXCLK16IN and
TXCLK16OUT of up to three parallel data words.
The FIFO circuitry indicates an overflow or underflow
condition by asserting FIFOERR high. This output can
be used to recenter the FIFO read/write pointers by
tieing it directly to the FIFORST input. The Si5600 will
also recenter the read/write pointers after the device’s
power on reset, external reset via RESET, and each
time the DSPLL transitions from an out of lock state to a
locked state (TXLOL transitions from low to high).
Parallel Input To Serial Output Relationship
The Si5600 provides the capability to select the order in
which data on the parallel input bus is transmitted
serially. Data on this bus can be transmitted MSB first or
LSB first depending on the setting of TXMSBSEL. If
TXMSBSEL is tied low, TXDIN0 is transmitted first
followed in order by TXDIN1 through TXDIN15. If
TXMSBSEL is tied high, TXDIN15 is transmitted first
followed in order by TXDIN14 through TXDIN0. This
feature simplifies board routing when ICs are mounted
on both sides of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5600 provides a control pin that can be
used to force TXDOUT to 0. By driving TXSQLCH low,
the high speed serial output, TXDOUT will be forced to
0. Transmit data squelching is disabled when the device
is in line loopback mode (LLBK = 0).
Clock Disable
The Si5600 provides a clock disable pin, TXCLKDSBL,
that is used to disable the high-speed serial data clock
output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of
CLKOUT are tied to 1.5 V through 50 Ω on-chip
resistors. This feature is used to reduce power
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Preliminary Rev. 0.31