SI5600 Datasheet, PDF (12/28 Pages) List of Unclassifed Manufacturers – SiPHY-TM OC-192/STM-64 SONET/SDH TRANSCEIVER

Si5600
Functional Description
The Si5600 transceiver is a low power, fully integrated
serializer/deserializer that provides significant margin to
all SONET/SDH jitter specifications. The device
operates from 9.9–10.7 Gbps making it suitable for OC-
192/STM-64, 10GbE, and OC-192/STM-64 applications
that use 15/14 forward error correction (FEC) coding.
The low speed receive/transmit interface uses LVDS I/
Os that are compliant to the Optical Interface Forum’s
SFI-4 standard.
Receiver
The receiver within the Si5600 includes a precision
limiting amplifier, high jitter tolerance clock and data
recovery unit (CDR), and 1:16 demultiplexer. In
addition, programmable data slicing and sampling
phase adjustment are provided to support bit-error-rate
(BER) optimization for long haul applications.
Limiting Amplifier
The Si5600 incorporates a high sensitivity limiting
amplifier with sufficient gain to directly accept the output
of transimpedance amplifiers. High sensitivity is
achieved by using a digital calibration algorithm to
cancel out amplifier offsets. This algorithm achieves
superior offset cancellation by using statistical
averaging to remove noise that may degrade more
traditional calibration routines.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are less than 20 mV
peak-to-peak differential. In addition, input signals that
exceed 1 V peak-to-peak differential will not cause any
performance degradation.
Loss-of-Signal (LOS) Detection
The limiting amplifier includes circuitry that generates a
loss-of-signal (LOS) alarm when the input signal
amplitude on RXDIN falls below an externally controlled
threshold. The Si5600 can be configured to drive the
LOS output low when the differential input amplitude
drops below a threshold set between ~10 mV and
50 mV pk-pk differential. Approximately 3 dB of
hysteresis prevents unnecessary switching on LOS.
The LOS threshold is set by applying a voltage between
0.20 V and 0.80 V to the LOSLVL input. The voltage
present on LOSLVL maps to an input signal threshold
as follows:
V_LOS
=
(_---V_{----L---O----S----L---V---L----–-----}0_---._--4_---x_----V_----R_-----E_----F_----)_-
15
+
30
mV
V_LOS is the differential pk-pk LOS threshold referred to
the RXDIN input, V_LOSLVL is the voltage applied to the
LOSLVL pin, and VREF is reference voltage output on
the VREF pin.
The LOS detection circuitry is disabled by tieing the
LOSLVL input to the supply (VDD). This forces the LOS
output high.
Slicing Level Adjustment
To support applications that require BER optimization,
the limiting amplifier provides circuitry that supports
adjustment of the 0/1 decision threshold (slicing level)
over a range of ±20 mV when referred to the internally
biased RXDIN input. The slicing level is set by applying
a voltage between 0.20 V and 0.80 V to the SLICELVL
input. The voltage present on SLICELVL sets the slicing
level as follows:
V_LEVEL
=
(_---V_{----S----L---I-C----E-----–----}0_---._--4_----x_---V_-----R_----E_-----F_----)
15
V_LEVEL is the slicing level referred to the RXDIN input,
V_SLICE is the voltage applied to the SLICE_LVL pin, and
VREF is reference voltage output on the VREF pin.
The slicing level adjustment may be disabled by tieing
the SLCLVL input to the supply (VDD). When slicing is
disabled, the slicing offset is set to 0.0 V relative to
internally biased input common mode voltage for
RXDIN.
Clock and Data Recovery (CDR)
The Si5600 uses an integrated CDR to recover clock
and data from a non-return to zero (NRZ) signal input on
RXDIN. The recovered data clock is used to regenerate
the incoming data by sampling the output of the limiting
amplifier at the center of the NRZ bit period. The
recovered clock and data is then deserialized by a 1:16
demultiplexer and output via a LVDS compatible low
speed interface (RXDOUT[15:0], RXCLK1, and
RXCLK2).
Sample Phase Adjustment
In applications where it is not desirable to recover data
by sampling in the center of the data eye, the Si5600
supports adjustment of the CDR sampling phase across
the NRZ data period. When sample phase adjustment is
enabled, the sampling instant used for data recovery
can be moved over a range of ±45° relative to the center
of the incoming NRZ bit period. Adjustment of the
sampling phase is desirable when data eye distortions
are introduced by the transmission medium.
The sample phase is set by applying a voltage between
0.20 V and 0.80 V to the PHASEADJ input. The voltage
present on PHASEADJ maps to sample phase offset as
follows:
12
Preliminary Rev. 0.31