C8051F340 Datasheet, PDF (99/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
10. Prefetch Engine
The C8051F340/1/2/3/4/5/6/7 family of devices incorporate a 2-byte prefetch engine. Because the access
time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch
engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at
a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running linear
code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full
speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next
set of code bytes is retrieved from FLASH memory. The FLRT bit (FLSCL.4) determines how many clock
cycles are used to read each set of two code bytes from FLASH. When operating from a system clock of
25 MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock cycle for
each read. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the FLRT bit
should be set to ‘1’, so that each prefetch code read lasts for two clock cycles.
SFR Definition 10.1. PFE0CN: Prefetch Engine Control
R
R
R/W
R
R
R
R
R/W
Reset Value
PFEN
FLBWE 00100000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xAF
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5: PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0: FLBWE: FLASH Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of two.
Rev. 0.5
99