C8051F340 Datasheet, PDF (33/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
4. Pinout and Package Definitions
Name
V_DD
GND
/RST/
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7
Pin Numbers
Type Description
48-pin 32-pin
10
6 Power In 2.7–3.6 V Power Supply Voltage Input.
Power 3.3 V Voltage Regulator Output. See Section 8.
Out
7
3
Ground.
13
9
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 11.
C2CK
C2D
P3.0 /
C2D
REGIN
VBUS
D+
D-
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D I/O _{Clock signal for the C2 Debug Interface.}
14
-
D I/O Bi-directional data signal for the C2 Debug Interface.
-
10 D I/O Port 3.0. See Section 15 for a complete description of Port
3.
D I/O
Bi-directional data signal for the C2 Debug Interface.
11
7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator.
12
8
D In VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
8
4
D I/O USB D+.
9
5
D I/O USB D–.
6
2 D I/O or Port 0.0. See Section 15 for a complete description of Port
A In 0.
5
1 D I/O or Port 0.1.
A In
4
32 D I/O or Port 0.2.
A In
3
31 D I/O or Port 0.3.
A In
2
30 D I/O or Port 0.4.
A In
1
29 D I/O or Port 0.5.
A In
48 28 D I/O or Port 0.6.
A In
47 27 D I/O or Port 0.7.
A In
Rev. 0.5
33