|
C8051F340 Datasheet, PDF (224/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family | |||
|
◁ |
C8051F340/1/2/3/4/5/6/7
SFR Definition 19.1. SCON1: UART1 Control
R/W
OVR1
Bit7
R/W
PERR1
Bit6
R
THRE1
Bit5
R/W
REN1
Bit4
R/W
TBX1
Bit3
R/W
RBX1
Bit2
R/W
R/W
Reset Value
TI1
RI1 00100000
Bit1
Bit0
Bit
Addressable
SFR Address: 0xD2
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
OVR1: Receive FIFO Overrun Flag.
This bit is used to indicate a receive FIFO overrun condition.
0: Receive FIFO Overrun has not occurred.
1: Receive FIFO Overrun has occurred (an incoming character was discarded due to a full
FIFO).
This bit must be cleared to â0â by software.
PERR1: Parity Error Flag.
When parity is enabled, this bit is used to indicate that a parity error has occurred. It is set to
â1â when the parity of the oldest byte in the FIFO does not match the selected Parity Type.
0: Parity Error has not occurred.
1: Parity Error has occurred.
This bit must be cleared to â0â by software.
THRE1: Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty - do not write to SBUF1.
1: Transmit Holding Register Empty - it is safe to write to SBUF1.
REN1: Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the
receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
TBX1: Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE1 is set to
â1â. This bit is not used when Parity is enabled.
RBX1: Extra Receive Bit.
RBX1 is assigned the value of the extra bit when XBE1 is set to â1â. If XBE1 is cleared to â0â,
RBX1 will be assigned the logic level of the first stop bit. This bit is not valid when Parity is
enabled.
TI1: Transmit Interrupt Flag.
Set to a â1â by hardware after data has been transmitted, at the beginning of the STOP bit.
When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the
UART1 interrupt service routine. This bit must be cleared manually by software.
RI1: Receive Interrupt Flag.
Set to â1â by hardware when a byte of data has been received by UART1 (set at the STOP bit
sampling time). When the UART1 interrupt is enabled, setting this bit to â1â causes the CPU
to vector to the UART1 interrupt service routine. This bit must be cleared manually by soft-
ware.
224
Rev. 0.5
|
▷ |