C8051F340 Datasheet, PDF (79/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
9.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 9.2.
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
RESERVED
0xFF
0x80
0x7F
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x1000
0x0FFF
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
0x0000
0x07FF
0x0400
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F340/1/2/3/4/5/6/7 implements 64k or
32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the
C8051F340/2/4/6 (64k version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to Section “12. Flash Memory” on page 109 for further details.
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