BC41B143A-DS-001PE Datasheet, PDF (85/102 Pages) List of Unclassifed Manufacturers – BlueCpre 4-ROM Single Chip Bluetooth v2.0 System with EDR

Device Terminal Descriptions
On reset and up to the time the PIO has been configured, PIO[2] will be tri-stated. Therefore, the developer must
ensure that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This
ensures that the TCXO is oscillating at start up.
10.11 RESET and RESETB
BlueCore4-ROM may be reset from several sources: RESET or RESETB pins, power on reset, a UART break
character or via a software configured watchdog timer.
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A
reset will be performed between 1.5 and 4.0ms following RESET being active. CSR recommends that RESET is
applied for a period greater than 5ms. The RESETB pin is the active low version of RESET and is ‘Ored’ on-chip
with the active high RESET with either causing the reset function.
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when
VDD_CORE rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-stated. The PIOs have weak
pull-downs.
Following a reset, BlueCore4-ROM assumes the maximum XTAL_IN frequency, which ensures that the internal
clocks run at a safe (low) frequency until BlueCore4-ROM is configured for the actual XTAL_IN frequency. If no
clock is present at XTAL_IN, the oscillator in BlueCore4-ROM free runs, again at a safe frequency.
BC41B143A-ds-001Pe
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
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