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BC41B143A-DS-001PE Datasheet, PDF (77/102 Pages) List of Unclassifed Manufacturers – BlueCpre 4-ROM Single Chip Bluetooth v2.0 System with EDR
Device Terminal Descriptions
10.7.8 PCM Timing Information
Symbol
Parameter
Min
Typ
Max
Unit
4MHz DDS generation.
128
Selection of frequency is
programmable, see
-
256
Table 10.11
512
fmclk
PCM_CLK frequency
48MHz DDS generation.
Selection of frequency is
programmable, see
2.9
-
Table 10.12 and
Section 10.7.10
-
PCM_SYNC frequency
-
8
tmclkh(1)
tmclkl(1)
PCM_CLK high
PCM_CLK low
4MHz DDS generation
980
-
4MHz DDS generation
730
-
-
PCM_CLK jitter
48MHz DDS generation
-
-
tdmclksynch
Delay time from PCM_CLK high to PCM_SYNC
high
-
-
tdmclkpout
Delay time from PCM_CLK high to valid PCM_OUT
-
-
tdmclklsyncl
Delay time from PCM_CLK low to PCM_SYNC low
(Long Frame Sync only)
-
-
tdmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC low
-
-
tdmclklpoutz
Delay time from PCM_CLK low to PCM_OUT high
impedance
-
-
tdmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT high
impedance
-
-
tsupinclkl
thpinclkl
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
30
-
10
-
Table 10.9: PCM Master Timing
-
kHz
-
kHz
-
kHz
-
ns
ns
21
ns pk-pk
20
ns
20
ns
20
ns
20
ns
20
ns
20
ns
-
ns
-
ns
Note:
(1) Assumes normal system clock operation. Figures will vary during low power modes, when system clock
speeds are reduced.
BC41B143A-ds-001Pe
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© Cambridge Silicon Radio Limited 2005
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