PT8R1202 Datasheet, PDF (8/26 Pages) List of Unclassifed Manufacturers – Bluetooth Digital Audio Streaming IC

Data Sheet
PT8R1202
PT Pericom Technology Inc.
Bluetooth Digital Audio Streaming IC
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Table 1. PLL mode set value for setting core frequency
XTALIN
12MHz
13MHz
16MHz
19.2MHz
Don’t use
Don’t use
PLL_MD1
Low
Low
High
High
96MHz
TESTCLK
PLL_MD0
Low
High
Low
High
Low
High
PLLSEL
Low
Low
Low
Low
High
High
CLKOUT
32MHz
42.7MHz
32MHz
42.7MHz
32MHz
42.7MHz
32MHz
42.7MHz
32MHz
TESTCLK
CLKSYS
96MHz
128MHz
96MHz
128MHz
96MHz
128MHz
96MHz
128MHz
96MHz
TESTCLK
Comment
Normal mode
Turbo mode
Normal mode
Turbo mode
Normal mode
Turbo mode
Normal mode
Turbo mode
Normal mode
TEST mode
2. If both PLL_MD0 and PLLSEL are high, the operation mode of PT8R1202 changes into TEST mode. This mode is used only for
manufacturing test purpose. In TEST mode, the boot mode will be used as indication of specific test mode. In normal mode, the boot
mode indicates the source of boot code to be fetched first PC.
Table 2. Boot mode set value for indicating the source of boot code fetch in normal mode
BTMD[1:0]
0
1
2
3
Name
Flash
Debug
reserved
NandFlash
Comment
Boot from external memory using FLASHCSB[0] signal
Wait for debug command through JTAG
Bood from NandFlash using smart media interface
The size of NandFlash is indicated by SSM pin. See note7 for more information.
Table 3. Boot mode set value for indicating the source of boot code fetch in test mode
BTMD[1:0]
0
1
2
3
Name
SCAN test
Codec test
Codec0 test
Codec1 test
Comment
Full scan test mode (manufacturing test purpose)
Analog audio external test mode (debugging purpose)
Audio left DAC and ADC test mode (manufacturing test purpose)
Audio right DAC and ADC test mode (manufacturing test purpose)
3. This pin should be low for normal operation. It is used only in manufacturing test.
4. PIN of MEMA[19:0] : A6, B7, A7, C7, D7, B8, A8, D8, A9, C8, D9, A10, B9, C9, B10, A11, A12, B11, B12, C11
5. PIN of MEMD[15:0] : F11, F12, G11, G12, H12, G10, H11, H10, J12, K12, J9, J11, J10, L12, K11, K10
6. In non byte access device such as flash memory(x16), these pin will be not connected.
7. This pin can be programmed to access the second NAND flash chip in addition to SM_CSB signal. With this pin, PT8R1202 can support
up to 4 Gb(512MB) NAND flash directly.
8. These pins can be used as multiple purposes by programming such as digital AMP output, UART flow control signal and alternative I2S
input. From R2.4, the default direction and signal usage is changed. The default configuration is the output of internal digital amplifier.
For the case of alternative I2S input mode, the sampling frequency of I2S input can be different to that of I2S output.
9. Internal audio codec is not recommended to use for both voice and audio. Instead of internal stereo sigma-delta DAC, we recommend to
use external voice and audio codec. From R2.6, EARA and EARB PAD are only dedicated to oscillator PAD for external sleep crystal.
10. PIN of SM_DATA[7:0] : K5, J5, M5, L5, K6, M6, J6, L6
11. These pins is only used at NandFlash boot mode. If BTMD is “11” which means on-chip processor boots from NandFlash, these pins are
used as size indication of external NandFlash. After the completion of boot, it is used as GPIO. Otherwise, it is always used as GPIO.
12. This signal can be programmed for embedded processor to be waked up from sleep or deep sleep power state.
13. Instead of dividing clock from XTALIN, this pin can be used as the low oscillator clock source as programming for extremely low
power consumption in stand-by state.
14. From R2.4, the default direction of this pin is output as SPDIF output signal.
15. PIN of VCC : G4, H4, H5, H6, H7, H8
16. PIN of VPP : F5, F6, F7, F8, G9, H9
17. PIN of VCC_GND : E4, F4, G5, G6, G7, G8
18. PIN of VPP_GND : E5, E6, E7, E8, E9, F9
PT0137(08/04)
8
Ver:4