PT8R1202 Datasheet, PDF (12/26 Pages) List of Unclassifed Manufacturers – Bluetooth Digital Audio Streaming IC

Data Sheet
PT8R1202
PT Pericom Technology Inc.
Bluetooth Digital Audio Streaming IC
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I/O Description
Off-chip memory interface
The external memory port comprises a 16bit data bus(MEMD[15:0]) and an 20bit address bus(MEMA[19:0]), thus addressing up to 2Mbytes
of off-chip code or data. Control signal WEB, REB, and multiple CSB(FLAHSCSB, SRAMCSB, IOCSB0 and IOCSB1) are provided, which
make it possible to use a variety of different memories, including flash memory, SRAM and ROM. For SRAM access, UBE and LBE signal
support byte access and memory interface block automatically handles control signals for 32bit word, 16bit half-word and 8bit byte access of
on-chip microcontroller memory operations. In standard Bluetooth application, only external 256KB flash memory is required in PT8R1202.
For additional Bluetooth application including several Bluetooth protocol stack which requires more data memory than internal SRAM of
PT8R1202, external SRAM is used for extended data memory of PT8R1202 on-chip microcontroller. The access time of each device can be
programmed and the wait cycle ranges 0 to 63 based on system clock, which is normally processor clock, that is CLKSYS. External flash can
be programmed via host interface by external host or self update by PT8R1202 on-chip RISC/DSP processor.
Because PT8R1202 on-chip RISC/DSP processor is based on harvard architecture, the address map of instruction and data access is difference.
Following table 1. shows the instruction address map and table 2. shows the data address map.
Table 4. Instruction address map
Address(24bit)*
0x000000~0x1FFFFF
0x200000~0x3FFFFF
0x400000~0x5FFFFF
0x600000~0x7FFFFF
0x800000~0x9FFFFF
Device
FLASH
-
SRAM
IO0
IO1
Attribute
read only
-
read only
read only
read only
Description
cacheable, scratch-pad memory or non-cacheable
reserved
cacheable, scratch-pad memory or non-cacheable
cacheable, scratch-pad memory or non-cacheable
cacheable, scratch-pad memory or non-cacheable
* This address space is based on byte addressing. There are addition extended two bits in the most significant bits(25th and 24th), and they are
used for the indication of section attribute. All instructions are checked whether they are cached in the scratch-pad memory first. Then, those
two bits are used to check the source of that instruction fetch. “00” indicates those section can be loaded only through on-chip instruction cache
with conventional two-way set associate policy. “01” indicates those section can be loaded only set0 region of on-chip instruction cache. “10”
indicates those section can be loaded only set1 region of on-chip instruction cache. “11” indicates those section can be loaded directly from
external memory without passing instruction cache. The address space of this internal scratch-pad memory is 0xA00000~0xA0BFFF for
XMEM and 0xC00000~0xC0BFFF for YMEM. The scratch memory is divided into four pages each size of which is 32KB with 9-bit
instruction tag which consists of 3-bit section attribute and the most significant 6-bit section address. On-chip RISC processor will check the
match by full associative comparison with four tag registers of internal scratch-pad memory first. Then, if that tag comparison is matched,
instruction will be fetched from internal scratch-pad memory. Otherwise, instruction will be fetch through on-chip instruction cache from
external flash memory region.
Table 5. Data address map
Address(23bit)*
0x000000~0x1FFFFF
Device
FLASH
0x200000~0x3FFFFF
0x400000~0x5FFFFF
-
SRAM
0x600000~0x7FFFFF
0x800000~0x9FFFFF
0xA00000~0xA07FFF
IO0
IO1
XMEM0
(32KB)
0xA08000~0xA0BFFF
XMEM1
(16KB)
0xA0C000~0xA0FFFF
XMEM2
(16KB)
0xC00000~0xC07FFF
YMEM0
(32KB)
Attribute
read/write
half-word, word
-
read/write
byte, half-word, word
read/write
byte, half-word, word
read/write
byte, half-word, word
read/write
byte, half-word, word
DSP memory (14M)
read/wrtie
byte, half-word, word
DSP memory (14M)
read/write
byte, half-word, word
read/write
byte, half-word, word
Description
z instruction code memory
z constant data memory
z accessible by on-chip DMA
reserved
z data memory
z fast fetch instruction code memory
z accessible by on-chip DMA
z I/O access
z accessible by on-chip DMA
z I/O access
z accessible by on-chip DMA
z data memory
z scratch-pad instruction memory
z SmartMedia™ FIFO
z accessible by DMA
z data memory
z scratch-pad instruction memory
z SmartMedia™ FIFO
z accessible by on-chip DMA
z data memory
z Bluetooth baseband FIFO,
z USB FIFO(0x20C000~0x20FFFF)
z accessible by on-chip DMA
z data memory
z scratch-pad instruction memory
PT0137(08/04)
12
Ver:4