PT8R1202 Datasheet, PDF (6/26 Pages) List of Unclassifed Manufacturers – Bluetooth Digital Audio Streaming IC

Data Sheet
PT8R1202
PT Pericom Technology Inc.
Bluetooth Digital Audio Streaming IC
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Pin Descriptions
Pin Name
PIN
I/O
TYPE
Description
DI(Digital Input, 3.3V), DO(Digital Output, 3.3V), DB(Digital Bidirectional, 3.3V), DP(Digital Programmable, 3.3V)
DCP(Digital Core Power, 1.8V), DPP(Digital Peripheral Power, 3.3V)
DCG(Digital Core Ground), DPG(Digital Peripheral Ground)
AAI(Analog Audio Input, 3.3V), AAO(Analog Audio Output, 3.3V), AAB(Analog Audio Bidirectional, 3.3V)
ACI(Analog Core Input, 1.8V), ACO(Analog Core Output, 1.8V), ACB(Analog Core Bidirectional, 1.8V)
AAP(Analog Audio Power, 3.3V), AAG(Analog Audio Ground)
ACP(Analog Core Power, 1.8V), ACG(Analog Core Ground)
BLUETOOTH INTERFACE : 12
TXACTIVE / GPA[0]
D4
RXACTIVE / GPA[1]
C1
TXDATA_EN / GPA[2]
E2
TXDATA / GPA[3]
D1
RXDATA / GPA[4]
E3
SYNCDECTECT / GPA[5]
E1
DATACLK / GPA[6]
F1
RFRESET / GPA[7]
F3
BLUERF_TCK / GPA[8]
F2
BLUERF_TMS / GPA[9]
G3
BLUERF_TDI / GPA[10]
G1
BLUERF_TDO / GPA[11]
G2
DO/ DP
DO / DP
DO / DP
DB / DP
DI / DP
DB / DP
DI / DP
DO / DP
DO / DP
DO / DP
DB / DP
DI / DP
active high
active high
active high
serial data
serial data
active high
clock
active high
clock
serial data
serial data
serial data
transmitter enable
receiver enable
timing reference of valid data
transmit data
receive data
indication of SYNC word detection
Phy reference data clock
Reset signal for external radio transceiver
a serial register interface clock
control signal of Phy’s TAP controller
Phy control register serial data output
Phy control register serial data input
CLOCK SIGNAL INTERFACE : 6
XTALIN
J8
XTALOUT
L9
PLL_MD1
M10
PLL_MD0
M11
PLLSEL
L10
CLKOUT / GPB[0]
L7
DI
clock
DO
clock
DI
control
DI / DO
DI
DO / DP
control
control pin
clock
Crystal input for on-chip PLL (see note1)
Crystal output
PLL mode control (see note1)
External, test clock input (see note1, 2)
PLL mode control (see note1)
Manufacturing test mode (see note2)
External clock source select signal (see note1,2)
clock out divided by a third of internal system clock (see note1)
TEST & DEBUG INTERFACE : 9
RESET
BTMD[1:0]
SCAN_EN
JTAG_TCK / GPC[4]
JTAG_TMS / GPC[5]
K8
M7, J7
C5
M8
K7
JTAG_RST / GPC[6]
L8
JTAG_TDI / GPC[7]
K9
JTAG_TDO / GPC[8]
M9
DI
DI / DP
DI
DI / DP
DI / DP
DI / DP
DI / DP
DO / DP
active low
control pin
control pin
clock
serial data
active low
serial data
serial data
reset signal
boot mode (see note2)
manufacturing test (see note3)
JTAG clock signal
JTAG test mode signal
JTAG reset signal
JTAG serial input data
JTAG serial output data
EXTERNAL MEMORY INTERFACE : 45
MEMA[19:0]
MEMD[15:0]
WEB
(see note4)
(see note5)
C10
REB
C12
UBE / GPB[1]
D11
LBE / GPB[2]
D10
FLASHCSB / GPB[3]
D12
SRAMCSB / GPB[4]
E10
IOCSB0 / GPB[5]
E11
IOCSB1 / SM_CSB1 / GPB[6]
E12
IOWAIT / GPB[7]
F10
UART & USB INTERFACE : 6
UARTTX / GPC[0]
H3
UARTRX / GPC[1]
H1
DIGAMP_L / UARTRTS /
AUDISCLK / GPC[2]
H2
DIGAMP_R / UARTCTS /
AUDILRCLK / GPC[3]
J4
D+
B4
D-
A4
DO
DB
DO
DO
DO / DP
DO / DP
DO
DO / DP
DO / DP
DO / DP
DI / DP
DO / DP
DI / DP
DO / DP
DO / DP
DB
DB
bus
bus
active low
active low
active low
active low
active low
active low
active low
active low
control pin
serial data
serial data
active low
active low
serial data
serial data
address bus for external memory
data bus for external memory
write enable signal for external memory
read enable signal for external memory
upper byte enable (see note6)
lower byte enable (see note6)
chip select for external flash memory
chip select for external SRAM memory
chip select for external I/O device0
chip select for external I/O device1 (see note7)
IO wait cycle extension indication signal
UART serial transmit data / USBOE
UART serial receive data / USBSPEED
UART RTS(Ready To Send) signal / USBVPO
AUDISCLK / DIGAMP_L (see note8)
UART CTS(Clear To Send) signal / USBVMO
AUDILRCLK / DIGAMP_R(see note8)
USB D+
USB D-
PT0137(08/04)
Ver:4
6