PT8R1202 Datasheet, PDF (7/26 Pages) List of Unclassifed Manufacturers – Bluetooth Digital Audio Streaming IC

Data Sheet
PT8R1202
PT Pericom Technology Inc.
Bluetooth Digital Audio Streaming IC
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Pin Name
PIN
I/O
TYPE
Description
DIGITAL AUDIO INTERFACE : 9
PCMOUT / GPD[0]
PCMIN / GPD[1]
PCMSYNC / GPD[2]
PCMCLK / GPD[3]
AUDSCLK / GPD[4]
AUDLRCLK / GPD[5]
AUDOUT / GPD[6]
AUDMCLK / GPD[7]
AUDIN / SPDIFIN/GPD[8]
J3
DO / DP serial data PCM 8kbps data out
J1
DI / DP serial data PCM 8kbps data input
J2
DP
clock
PCM 8KHz frame synchronization signal
K1
DP
clock
PCM bit data clock (128/256)
K2
DP
clock
audio serial data bit clock(64*fs)
L1
DP
clock/
audio left/right sync clock(fs)
L2
DO / DP serial data audio serial data output
M1
DP
clock
audio oversampled clock(256/384*fs)
K3
DI / DP serial data
audio serial data input
ANALOG AUDIO INTERFACE : 6 (see note9)
MIC_IN
MICGS
VMID
VREF
EARA
EARB
B2
AAI
analog
A1
AAO
analog
C3
AAO
analog
C2
AAO
analog
C4
AAO
analog
B1
AAO
analog
Reserved
Reserved
Reserved
Reserved
Sleep crystal(32.768kHz) XTALIN
Sleep crystal(32.768kHz) XTALOUT
SMARTMEDIA INTERFACE : 14
SM_CSB / GPE[0]
SM_CLE / GPE[1]
SM_ALE / GPE[2]
SM_WE / GPE[3]
SM_OE / GPE[4]
SM_RB / GPE[5]
SM_DATA[7:0] /GPF[7:0]
L3
M2
M3
K4
M4
L4
(see note10)
DO / DP
DO / DP
DO / DP
DO / DP
DO / DP
DI / DP
DB
active low
active low
active low
active low
active low
control pin
bus
Smartmedia chip select
Smartmedia command latch enable
Smartmedia address latch enable
Smartmedia write enable
Smartmedia read enable
Smartmedia ready signal
Smartmedia data/address bus
GPIO INTERFACE : 7
GPG[0] / IRQ0 / SSM1
GPG[1] / IRQ1
GPG[2] / WAKEUP
GPG[3] / SSM0
GPG[4] / CLK32K
SPDIFO / GPG[5]
D6
DI / DP active high external interrupt request0 (see note11)
B6
DI / DP active high external interrupt request1 / USBVPI
C6
DI / DP active high external wake up signal (see note12) / USBRCV
A5
DO / DP clock
Size indicator at Smartmedia boot (see note11) / USBVMI
D5
DB / DP signal
External RTC clock(32kHz) input (see note13)
B5
DO / DP signal
SPDIF output / USBSUSPND (see note14)
POWER SUPPLIES : 31
SPLL_VCC(1)
SPLL_GND(1)
APLL_VCC(1)
APLL_GND(1)
ACODEC_VCC(1)
ACODEC_GND(2)
VCC(6)
VCC_GND(6)
VPP(6)
VPP_GND(6)
L11
M12
D3
D2
A2
A3, B3
(see note15)
(see note16)
(see note17)
(see note18)
ACP
ACG
ACP
ACG
AAP
AAG
DCP
DCG
DPP
DPG
power
ground
power
ground
power
ground
power
ground
power
ground
supply for system PLL (1.8V)
ground for system PLL
supply for audio PLL (1.8V)
ground for audio PLL
supply for combo audio codec (3.0V)
ground for combo audio codec
power for digital core block (1.8V)
ground for digital core block
supply for digital peripheral blocks (3.3V)
ground for digital peripheral blocks
Note :
1. PT8R1202 use two main clocks for core operation and peripheral operation. Both clocks can be generated from on-chip PLL or
individually pumped from external clock source. The clock for processor operation, named CLKSYS, can be variable by application
requirement or dynamic power management, but the clock for peripheral operation must be fixed as 48MHz for USB and audio interface
and 32MHz for others. The PLL in the PT8R1202 supports 12MHz, 13MHz, 16MHz, or 19.2MHz as reference clock. Following table
shows the configuration of PT8R1202 clock generation block. For using internal clock from on-chip PLL, PLLSEL must be set “0”.
When using internal clock from on-chip PLL, PT8R1202 can change the operating frequency of on-chip processor up to 128MHz turbo
mode. The default operation mode is normal execution at 96MHz operating frequency and it can be changed into turbo mode by software.
However, in the case of using external clock source, it does not support turbo mode.
PT0137(08/04)
7
Ver:4