DM9102D Datasheet, PDF (8/70 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHEMET NIC CONTROLLER

88
89
90
5.4 Network Interface
Pin No.
128LQFP
105,106
109,110
5.5 Miscellaneous Pins
Pin No.
128LQFP
75
84
83
36
71
8
FDX#
SPD100#
SPD10#
Pin Name
RXI+
RX-
TXO+
TXO-
mode 0 = Link and traffic LED. Active low to indicate normal
link, and it will flash as a traffic LED when transmitting or
receiving.
mode 1 = traffic LED only
O/D LED Output Pin, Active Low
mode 0 = Full duplex LED
mode 1 = Full duplex LED
O/D LED Output Pin, Active Low
mode 0 = 100Mbps LED
mode 1 = 100Mbps LED
O/D LED Output Pin, Active Low
mode 0 = 10Mbps LED
mode 1 = Link LED
I/O
Description
I 100M/10Mbps Differential Input Pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of receiving
100BASE-TX MLT-3 or 10BASE-T Manchester encoded
data.
O 100M/10Mbps differential output pair.
These two pins are differential output pair for 100BASE-TX
and 10BASE-T. This output pair provides controlled rising and
falling time, designed to filter the transmitter’s output.
Pin Name
IDSEL2
REQ2#
GNT2#
CLOCKRUN#
TEST2
I/O
Description
O PCI IDSEL 2.
When this pin is pulled high, the PCI multiple function is
present, and it act as PCI IDSEL2 function.
O PCI Request 2
If the PCI multiple function mode is selected, this pin act as the
PCI REQ2# function.
I PCI GNT2#
If the PCI multiple function mode is selected, this pin act as
GNT2# function.
When this pin is pulled high, the DM9102D is in LED mode 1
otherwise the led mode 0 is selected.
I/O Clockrun#
The clockrun# signal is used by the system to pause or slow
down the PCI clock signal. It is used by the DM9102D to
enable or disable suspension or restart of the PCI clock. When
the CLOCKRUN# pin is not used, this pin should be connected
to an external pulled down resistor.
I TEST mode control 2
In normal operation, tie high to this pin.
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005