DM9102D Datasheet, PDF (31/70 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHEMET NIC CONTROLLER

6.2.12 Sample Frame Access Register (CR13) (reference to section 7.5 Power Management)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register General definition
bit8 ~ 3 R/W
TxFIFO Transmit FIFO access port
32H
R/W
RxFIFO Receive FIFO access port
35H
R/W
DiagReset General reset for diagnostic pointer port 38H
W
6.2.13 Sample Frame Data Register (CR14) (reference to section 7.5 Power Management)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6.2.14 Watchdog and Jabber Timer Register (CR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
31
30
29
28
27
26:15
14
Name
TXSUMC
IPSUM
TCPSUM
UDPSUM
RXSUM
Reserved
TXP0
13
TXPF
12:11 Reserved
10
FLCE
9
RXPS
8
Reserved
7
RXPCS
6
VLAN
Default
0,WO
0,WO
0,WO
0,WO
0,WO
0,RO
0,RW
0,RW
0,RO
0,RW
0,R/C
0,RO
0,RO
0,RW
Description
in transmit, generate IP/TCP/UDP chksum depend-on TX desc. control
in transmit, generate IP chksum to all packets
in transmit, generate TCP chksum to all packets
in transmit, generate UDP chksum to all packets
In receiving, report IP/TCP/UDP checksum status to RDES0
Reserved
Transmit pause packet
Set to transmit pause packet with pause timer = 0000h, this bit will be cleared if the
pause packet had transmitted.
Transmit pause packet
Set to transmit pause packet with pause timer = FFFFh, this bit will be cleared if the
pause packet had transmitted.
Reserved
Flow Control Enable
Set to enable the decode of the pause packet.
The latched status of the decode of the pause packet.
Reserved.
It is set to indicate that the current pause timer of pause packet is not down count to
zero yet.
VLAN length Capability Enable
It is set to enable the VLAN length mode and will not report the frame_too_long bit
status to RDES0 if receive packet size under 1526-byte.
Preliminary datasheet
31
Version: DM9102D-DS-P02
Jan. 14, 2005