DM9102D Datasheet, PDF (35/70 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHEMET NIC CONTROLLER

The PHY Identifier Register#1 and Register#2 work together in a single identifier of the DM9102D. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number.
DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
15:.0
Name
OUI_MSB
Default
Description
<0181H>, OUI Most Significant Bits:
RO/P This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register
respectively. The most significant two bits of the OUI are ignored (the IEEE
standard refers to these as bit 1 and 2)
6.3.4 PHY Identifier Register #2 (PHYIDR2) - 3
Bit
Name
Default
Description
15:10
OUI_LSB <101110>, OUI Least Significant Bits:
RO/P Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register
respectively
9:.4
VNDR_MDL <001010>, Vendor Model Number:
RO/P Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit
9)
3:0
MDL_REV <0000>, Model Revision Number:
RO/P Four bits of vendor model revision number mapped to bit 3 to 0 (most
significant bit to bit 3)
6.3.5 Auto-negotiation Advertisement Register (ANAR) – 4
This register contains the advertised abilities of this DM9102D device as they will be transmitted to its link partner during
Auto-negotiation.
Bit
Name
Default
Description
15
NP
0,RO/P Next Page Indication:
0=No next page available
1=Next page available
The DM9102D has no next page, so this bit is permanently set to 0
14
ACK
0,RO Acknowledge:
1=Link partner ability data reception acknowledged
0=Not acknowledged
The DM9102D's Auto-negotiation state machine will automatically control this
bit in the outgoing FLP bursts and set it at the appropriate time during the
Auto-negotiation process. Software should not attempt to write to this bit.
13
RF
0, RW Remote Fault:
1=Local Device senses a fault condition
0=No fault detected
12:11
Reserved
00, RW Reserved:
Write as 0, ignore on read
10
FCS
0, RW Flow Control Support:
1=Controller chip supports flow control ability.
0=Controller chip doesn’t support flow control ability.
9
T4
0, RW 100BASE-T4 Support:
1=100BASE-T4 is supported by the local device.
0=100BASE-T4 is not supported.
The DM9102D does not support 100BASE-T4 so this bit is 0 permanently
8
TX_FDX
1, RW 100BASE-TX Full Duplex Support:
1=100BASE-TX Full Duplex is supported by the local device.
0=100BASE-TX Full Duplex is not supported.
Preliminary datasheet
35
Version: DM9102D-DS-P02
Jan. 14, 2005