DM9102D Datasheet, PDF (52/70 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHEMET NIC CONTROLLER

The operational sequence from D0 to D3 should be:
Stop TX/RX process Æ wait for entering stop state Æ set
test mode, CR6<28:25> = 0011 Æ programming FIFO
contents Æ exit test mode Æ enter D3 (hot) state
The sample frame data comparison is completed when the
received frame data has exceeded the programmed frame
length or when the whole packet has been fully received.
The operation procedure is shown below.
CR13: Sample Frame Access Register
Name
General definition
TxFIFO
RxFIFO
Transmit FIFO access port
Receive FIFO access port
DiagReset General reset for diagnostic pointer port
Bit8:3
32h
35h
38h
Type
R/W
RW
RW
In DiagReset port there are 7 bits:
Bit 0: Clear TX FIFO write_ address to 0
Bit 1: Clear TX FIFO read_ address to 0
Bit 2: Clear RX FIFO write_ address to 0
Bit 3: Clear RX FIFO read_ address to 0
Bit 4: Reserved
Bit 5: Set TX FIFO write_ address to 080H
Bit 6: Set RX FIFO write_ address to 080H
52
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005