DM9102D Datasheet, PDF (28/70 Pages) List of Unclassifed Manufacturers – SINGLE CHIP FAST ETHEMET NIC CONTROLLER

8
RXPSE
7
RXDUE
6
RXCIE
5
TXFUE
4 Reserved
3
TXJTE
2
TXDUE
1
TXPSE
0
TXCIE
0,RW
0,RW
0,RW
0,RW
0,RO
0,RW
0,RW
0,RW
0,RW
Receive Process Stopped Enable
When set together with CR7<15> and CR5<8>. This bit is set to enable the
interrupt of receive process stopped condition.
Receive Buffer Unavailable Enable
When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of
receive buffer unavailable condition.
Receive Complete Interrupt Enable
When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of
receive process complete condition.
Transmit FIFO Underrun Enable
When set together with CR7<15>, CR5<5>, it will enable the interrupt of transmit
FIFO underrun condition.
Reserved
Transmit Jabber Expired Enable
When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of
transmit Jabber Timer Expired condition.
Transmit Buffer Unavailable Enable
When this bit and CR7<16>, CR5<2> are set together, the interrupt of transmit
buffer unavailable is enabled.
Transmit Process Stopped Enable
When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt
of the transmit process to stop.
Transmit Complete Interrupt Enable
When this bit and CR7<16>, CR5<0> are set, the transmit interrupt is enabled.
6.2.9 Statistical Counter Register (CR8)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
Name
31
ROCO
30:25 Reserved
24:17 RXDU
16
RXPS
15:7 Reserved
6:0
RXCI
Default
0,RO/C
0,RO
0,RO/C
0,RO/C
0,RO
0,RO/C
Description
Receive Overflow Counter Overflow
This bit is set when the Purged Packet Counter (RXDU) has an overflow condition.
Reserved
Receive Purged Packet Counter
This is a statistic counter to indicate the purged received packet counts upon FIFO
overflow.
Receive Missed Counter Overflow
This bit is set when the Receive Missed Frame Counter (RXCI) has an overflow
condition.
Reserved
Receive Missed Frame Counter
This is a statistic counter to indicate the Receive Missed Frame Count when there
is a host buffer unavailable condition for receive process.
6.2.10 Management Access Register (CR9)
28
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005