AC1040F Datasheet, PDF (8/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Phy Address Pins
Pin Name
PHYAD_ST
Pin #
47
PHYAD [4]
88
PHYAD [3]
89
PHYAD [2]
90
Type
I/O,D
I/O
I/O
I/O
Description
1 at reset = 0-XXX00, 1-XXX01, 2-XXX10, 3-XXX11
0 at reset = 0-XXX01, 1-XXX10, 2-XXX11, 3-XXX00
PHY Address [4:2]. These pins set the three MSB’s for SMI PHY address.
PHYAD [1:0] are internally wired to four ports. (See PHYAD_ST)
The PHYAD will also determine the scramble seed, this will help to reduce EMI
when there are multiple ports switching at the same time.
Mode Pins
Pin Name
FX_DIS
TP125
FORCE100
SCRAM_EN
ANEGA
BURN_IN*
Pin #
91
93
43
38
39
40
Type
Description
I/O FX Disable. Pulled low upon reset will put port 3 in 100FX mode.
I/O Transformer Ratio. Pulled low upon reset will select transmit transformer ratio
to be 1.25:1. Pulled high is 1:1 transformer.
I/O FORCE100: Force 100Base-X Operation. When this signal is pulled high and
ANENGA is low upon reset, all ports will be forced to 100Base-TX operation.
When asserted low and ANENGA is low, all ports are forced to 10Base-T
operation. When ANENGA is high, FORCE100 has no effect on operation.
I/O Scrambler Enable. Pulled low upon reset will bypass the scrambler. Pulled high
is scrambler enabled.
I/O Auto-Negotiation Ability. Asserted high means auto-negotiation enable while
low means manual selection through FDXEN, F100.
I/O Burn-In mode. Burn-in mode for reliability assurance control. This is reserved
for internal testing only.
LED Pins
Pin Name
LEDDPX[0]
LEDDPX[1]
LEDDPX[2]
LEDDPX[3]
LEDACT_LNK[0]
LEDACT_LNK[1]
LEDACT_LNK[2]
LEDACT_LNK[3]
LEDSPD[0]
LEDSPD[1]
LEDSPD[2]
LEDSPD[3]
Pin # Type
Description
91 I/O,U Port[n] Duplex LED. Active state indicates Full Duplex or Collision in Half
88 I/O,U Duplex mode.
41 I/O,U
38 I/O,U
92 I/O,U Port[n] Activity/Link LED. Active state indicates a valid link. When there is
89 I/O,U receive or transmit activity, LED will toggle between high and low for 30 ms
42 I/O,U interval.
39 I/O,U
93 I/O,U Port[n] Speed LED. Active state indicates 100Base-TX mode.
90 I/O,U
43 I/O,U
40 I/O,U
Polarity of LEDs is determined by polarity of mode pins. See LED example
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Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 3.2
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