AC1040F Datasheet, PDF (13/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
data stream and set the data boundaries. The transmit
clock is locked to the 50 MHz clock input (RMII) or
25 MHz clock input (MII) while the receive clock is
locked to the incoming data streams. When initial
lock is achieved, the PLL switches to the data stream,
extracts the 125 MHz clock, and uses it for the bit
framing for the recovered data. The recovered 125
MHz clock is also used to generate the 25 MHz
MII_RXC (MII). The PLL requires no external
components for its operation and has high noise
immunity and low jitter. It provides fast phase
alignment and locks to data in one transition. Its
data/clock acquisition time after power-on is less than
60 transitions. The PLL can maintain lock on run-
lengths of up to 60 data bits in the absence of signal
transitions. When no valid data is present, i.e. when
the SD is de-asserted, the PLL will switch and lock
on to REFCLK. This provides a continuously running
MII_RXC (MII). At the PCS interface, the 5 bit data
RXD[4:0] is synchronized to the 25 MHz RX_CLK.
Decoder/De -scrambler
The de-scrambler detects the state of the transmit
Linear Feedback Shift Register (LFSR) by looking
for a sequence representing consecutive idle codes.
The de-scrambler acquires lock on the data stream by
recognizing IDLE bursts of 30 or more bits and locks
its frequency to its de-ciphering LFSR.
Once lock is acquired, the device can operate with an
inter-packet-gap (IPG) as low as 40 nS. However,
before lock is acquired, the de-scrambler needs a
minimum of 270 nS of consecutive idles in between
packets in order to acquire lock.
The de-ciphering logic also tracks the number of
consecutive errors received while the RX_DV is
asserted. Once the error counter exceeds its limit
currently set to 64 consecutive errors, the logic as-
sumes that the lock has been lost, and the de-cipher
circuit resets itself. The process of regaining lock
will start again.
Stream cipher de-scrambler is not used in the
100Base-FX and the 10Base-T modes.
Link Monitor
Signal level is detected through a squelch detection
circuitry. A signal detect (SD) circuit allows the
equalizer to assert high whenever the peak detector
detects a post-equalized signal with peak to ground
voltage greater than 400 mV. This is approximately
40% of a normal signal voltage level. In addition, the
energy level must be sustained for longer than 2~3
µS in order for the signal detect signal to stay on. The
SD gets de-asserted approximately 1~2 µs after the
energy level drops consistently below 300 mV from
peak to ground.
The link signal is forced low during a local loopback
operation (Loopback register bit is set) and forced to
high when a remote loopback is taking place
(EN_RPBK is set).
In forced 100Base-TX mode, when a cable is
unplugged or no valid signal is detected on the
receive pair, the link monitor enters in the “link fail”
state and NLP's are transmitted. When a valid signal
is detected for a minimum period of time, the link
monitor enters Link Pass State and transmits MLT-3
signal.
100BASE-FX
When port 3 is configured to run in 100Base-FX
mode, either through hardware configuration or
software configuration (100Base-FX does not support
ANeg) the Phy will support all the features and
parameters of the industry standards.
Transmit Function
The serialized data bypasses the scrambler and 4B/5B
encoder in FX mode. The output data is NRZI PECL
signals. The PECL level signals are used to drive the
Fiber-transmitter.
Receive Function
In 100Base-FX mode, signal is received through the
PECL receiver inputs, and directly passed to the
clock recovery circuit for data/clock extraction. In
FX mode, the scrambler/de-scrambler cipher function
is bypassed.
Link Monitor
In 100Base-FX mode, the external fiber-optic
receiver performs the signal energy detection
function and communicates this information directly
to the Phy’s SDP pin.
Far-End-Fault-Indication (FEFI)
ANeg provides the mechanism to inform the link
partner that a remote fault has occurred. However,
ANeg is disabled in the 100Base-FX applications. An
alternative in-band signaling function (FEFI) is used
to signal a remote fault condition. FEFI is a stream of
84 consecutive ones followed by one logic zero. This
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