AC1040F Datasheet, PDF (10/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
FUNCTIONAL DESCRIPTION
The AC104QF physical layer device (Phy) integrates
the 100Base-X and 10Base-T functions in a single
four port chip that is used in Fast Ethernet 10/100
Mbps applications. The 100Base-X section consists
of PCS, PMA, and PMD functions, and the 10Base-T
section consists of Manchester ENDEC and
transceiver functions. The device performs the
following functions:
Phy when there is valid data on the transmit bus. In
100M mode the Phy will read 2 bits from TXD[1:0]
for each cycle of REFCLK. In 10M mode the Phy
will read 2 bits of data from TXD[1:0] every 10^th
cycle of REFCLK.
The Serial Management Interface (SMI) is shared
between all ports in the Phy. This totals 7 pins per
port plus 3 per Phy, whereas MII has 18 pins per port.
• 4B/5B
• MLT3
• NRZI
• Manchester Encoding and Decoding
• Clock and Data Recovery
• Stream Cipher Scrambling / De-Scramb ling
• Adaptive Equalization
• Line Transmission
• Carrier Sense
• Link Integrity Monitor
• Auto-Negotiation (ANeg)
• RMII MAC connectivity
• MII Management Function
SMI
The Phy’s internal registers are accessible only
through the MII 2-wire Serial Management Interface
(SMI). MDC is a clock input to the Phy which is
used to latch in or out data and instructions for the
Phy. The clock can run at any speed from DC to 25
MHz. MDIO is a bi-directional connection used to
write instructions to, write data to, or read data from
the Phy. Each data bit is latched either in or out on
the rising edge of MDC. MDC is not required to
maintain any speed or duty cycle, provided no half
cycle is less than 20ns and that data is presented
synchronous to MDC.
It also provides an RMII consortium compatible
Reduced Media Independent Interface (RMII) to
communicate with an Ethernet Media Access
Controller (MAC). Selection of 10 or 100 Mbps
operation is based on the settings of internal Serial
Management Interface registers or determined by the
on-chip ANeg logic. The device can operate in 10 or
100 Mbps with full duplex or half-duplex mode on a
per port basis. Port 3 can also be configured for
100Base-FX.
MDC/MDIO are a common signal pair to all ports on
a design. Therefore, each port needs to have its own
unique Physical Address. The Physical Address of
the Phy is set using the pins defined as PHYAD[4:2].
These input signals are strapped externally and
sampled as reset is negated. PHYAD[1:0] are
addressed for each port internal to the Phy. Internal
addresses are either 00, 01, 10, 11 or 01, 10, 11, 00
depending on the polarity of PHYAD_ST during
reset.
MAC INTERFACE
RMII
The Reduced Media Independent Interface (RMII) is
used to connect the Phy with the MAC. The PHY
and MAC obtain their clock from a common 50 MHz
source, such as a clock oscillator. This clock is
shared by all ports within the Phy for transmitting
and receiving data on 2 individual 2-bit data buses.
CRS and RXDV are muxed together to indicate to the
MAC when there is valid data on the receive bus. In
100M mode RXD[1:0] is sampled on every cycle of
REFCLK. In 10M mode RXD[1:0] is sampled on
every 10^th cycle of REFCLK. RXER is generated by
the Phy to indicate a receive error to the MAC.
TX_EN is generated by the MAC to indicate to the
At idle, the PHY is responsible to pull MDIO line to
a high state. Therefore, a 1.5K Ohms resistor is
required to connect MDIO line to Vcc. The PHYAD
can be reprogrammed via software. A detailed
definition of the Serial Management registers
follows.
At the beginning of a read or write cycle, the MAC
will send a continuous 32 bits of one at the MDC
clock rate to indicate preamble. A zero and a one
will follow to indicate start of frame. A read OP
code is a one and a zero, while a write OP code is a
zero and a one. These will be followed by 5 bits to
indicate PHY address and 5 bits to indicate register
address. Then 2 bits follow to allow for turn around
time. For read operation, the first bit will be high
impedance. Neither the PHY nor the station will
assert this bit. During the second bit time, the PHY
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