AC1040F Datasheet, PDF (15/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Disable bit is cleared, the Phy has the ability to detect
the fact that either 8 NLPs or a burst of FLPs are
inverted and automatically reverse the receiver’s
polarity. The polarity state is stored in the Reverse
Polarity bit.
If the Auto Polarity Disable bit is set, then the
Reverse Polarity bit can be written to force the
polarity reversal of the receiver.
INITIALIZATION AND SETUP
HARDWARE CONFIGURATION
Several different states of operation can be chosen
through hardware configuration. External pins may
be pulled either high or low at reset time. The
combination of high and low values determines the
power on state of the device.
Many of these pins are multi-function pins which
change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states of operation can be chosen
through software configuration. Please refer to the
SMI section as well as the Register Descriptions.
LEDs
Each of the 4 ports has 3 individual LED outputs
available to indicate Speed, Duplex/Collision, and
Link/Activity. These multi-function pins are inputs
during reset and LED output pins thereafter. The
level of these pins during reset determines their
active output states. If a multi-function pin is pulled
up during reset to select a particular function, then
that LED output would become active low, and the
LED circuit must be designed accordingly, and vice
versa. (See LED Configuration.)
through hardware configuration. There is no support
for Auto-Negotiation of the FX interface.
Not all of the above combinations are possible due to
limitations of the environment and the 802.3
standards. Legitimate operating states are:
• 10Base-T Half Duplex
• 10Base-T Full Duplex
• 100Base-TX Half Duplex
• 100Base-TX Full Duplex
• 100Base-FX Half Duplex (Port 3 only)
• 100Base-FX Full Duplex (Port 3 only)
Only port 3 supports 100Base-FX.
The Phy can be hardware configured to force any one
of the above-mentioned modes. By forcing the
mode, the Phy will only run in that mode, hence
limiting the locations where the product will operate.
The Phy is able to negotiate its mode of operation in
the twisted pair environment using the Auto-
Negotiation mechanism defined in the clause 28 of
IEEE 802.3u specification. ANeg can be enabled or
disabled by hardware (ANEGA pin) or software
(Reg. 0.12) control. When the ANeg is enabled, the
Phy chooses its mode of operation by advertising its
abilities and comparing them with the ability received
from its link partner. It can be configured to ad-
vertise 100Base-TX or 10Base-T operating in either
full or half duplex.
Register 4 contains the current capabilities, speed and
duplex, of the Phy, determined through hardware
selects or chip defaults. The contents of Reg. 4 is
sent to its link partner during the ANeg process using
Fast Link Pulses (FLPs). An FLP is a string of 1s and
0s, each of which has a particular meaning, the total
of which is called a Link Code Word. After reset,
software can change any of these bits from 1 to 0 and
back to 1, but not from 0 to 1. Therefore, the
hardware has priority over software.
AUTO-NEGOTIATION
By definition the 10/100 Transceiver is able to run at
either 10Mbps over Twisted Pair Copper (10Base-T),
100Mpbs over Twisted Pair Copper (100Base-TX) or
100Mpbs over Fiber Optics (100Base-FX). In
addition the Phy is able to run in either half duplex
(repeater mode) or full duplex. To determine the
operational state, the Phy has hardware selects and
software selects while also supporting Auto-
Negotiation and Parallel Detection. To run in
100Base-FX mode, the selection must be done
When ANeg is enabled, the Phy sends out FLPs
during the following conditions:
• power on
• link loss
• restart ANeg command by software
During this period, the Phy continually sends out
FLPs while monitoring the incoming FLPs from the
link partner to determine their optimal mode of
operation. If FLPs are not detected during this phase
of operation, Parallel Detection mode is entered (see
below).
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Document Revision 4.0
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