88E1111 Datasheet, PDF (78/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

88E1111
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 34 is an example of a read operation.
Table 34: Serial Management Interface Protocol
32-Bit
Start of
Preamble Frame
11111111 01
OpCode
Read =
10
Write = 01
5-Bit
PHY
Device
Address
10
01100
5-Bit
PHY Reg-
ister
Address
(MSB)
00000
2-Bit
Turn
around
Read = z0
Write = 10
z0
16-Bit
Data Field
0001001100000000
Idle
11111111
2.9.1 Extended Register Access
MDC/MDIO protocol only supports 32 registers. Since the 88E1111 device has more than 32 registers, a paging
scheme is used to address more than 32 registers. The different pages might be accessed automatically based on
the operating mode or they can be selected by setting bit in other registers. For example, Register 29 sets the
applicable page of Register 30. Register 22 is used to select the different pages of various registers. See Section
3. "Register Description" on page 117 for details.
2.9.2 Preamble Suppression
The 88E1111 device is permanently programmed for preamble suppression. A minimum of one idle bit is required
between operations.
Doc. No. MV-S100649-00, Rev. E
Page 78
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2004 Marvell
November 19, 2004, Advance