88E1111 Datasheet, PDF (128/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

88E1111
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 56: Control Register - Fiber (Continued)
Page 1, Register 0
Bits Field
9
Restart Fiber
Auto-Negotia-
tion
8
Fiber Duplex
Mode
Mode HW
Rst
R/W,
0x0
SC
R/W
See
Descr
SW
Rst
SC
Update
Description
Auto-Negotiation automatically restarts after hardware
or software reset regardless of whether or not the restart
bit (0_1.9) is set.
The bit is set when Auto-Negotiation is Enabled or Dis-
abled in 1.0.12
1 = Restart Auto-Negotiation Process
0 = Normal operation
Changes to this bit are disruptive to the normal opera-
tion; therefore, any changes to these registers must be
followed by a software reset to take effect.
A write to this register bit does not take effect until any
one of the following also occurs:
Software reset is asserted (Register 0.15)
Restart Auto-Negotiation is asserted (Register 0_1.9)
Power down (Register 0.11) transitions from power
down to normal operation
Upon hardware reset this bit defaults as follows:
ANEG[3:0]
Bit 0_1.8
00x1
1
1xxx
1
all other configurations 0
7
Collision Test
R/W
6
Speed Selec- RO
tion (MSB)
5:0
Reserved
0x0
Always
1
0x0
Always
1
1 = Full-duplex
0 = Half-Duplex
Setting this bit to 1 will cause the COL pin to assert
whenever the TX_EN pin is asserted.
This bit is identical to 0_0.7.
1 = Enable COL signal test
0 = Disable COL signal test
bit 6, 13
10 = 1000 Mbps
These bits must be read and left unchanged when per-
forming a write.
Doc. No. MV-S100649-00, Rev. E
Page 128
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2004 Marvell
November 19, 2004, Advance