88E1111 Datasheet, PDF (53/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Functional Description
MAC Interfaces
Figure 10: RGMII Signal Diagram
MAC
RGMII Interface
TXC
TX_CTL
TD[3:0]
RXC
RX_CTL
RD[3:0]
GTX_CLK
TX_EN
TXD[3:0]
PHY
RX_CLK
RX_DV
RXD[3:0]
2.2.3.1 10/100 Mbps Functionality
This interface can be used to implement 10/100 Mbps Ethernet Media Independent Interface (MII) by reducing the
clock rate to 25 MHz for 100 Mbps operation, and 2.5 MHz for 10 Mbps. The GTX_CLK (TXC) signal is always
generated by the MAC, and the RX_CLK (RXC) signal is generated by the PHY.
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the
transition from the free running clock to a data synchronous clock domain. When the speed of the PHY changes,
a similar stretching of the positive or negative pulse is allowed. No glitching of the clocks is allowed during speed
transitions.
The MAC must hold TX_EN (TX_CTL) low until the MAC has ensured that TX_EN (TX_CTL) is operating at the
same speed as the PHY.
2.2.3.2 TX_ER and RX_ER Coding
See the RGMII Specifications for definitions of RX_CTL, TX_CTL, and in band status coding.
In RGMII mode, Register 20.15 is the register bit used to block carrier extension.
Copyright © 2004 Marvell
November 19, 2004, Advance
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S100649-00, Rev. E
Page 53