IT8702F Datasheet, PDF (74/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
Bit
Description
4 Enables the generation of an SMI# due to FAN Controller’s IRQ (EN_ECIRQ).
3 Enables the generation of an SMI# due to Parallel Port’s IRQ (EN_PIRQ).
2 Enables the generation of an SMI# due to Serial Port 2’s IRQ (EN_S2IRQ).
1 Enables the generation of an SMI# due to Serial Port 1’s IRQ (EN_S1IRQ).
0 Enables the generation of an SMI# due to FDC’s IRQ (EN_FIRQ).
8.11.19 SMI# Control Register 2 (Index=F1h, Default=00h)
Bit
Description
7 Forces to clear all the SMI# status register bits, non-sticky.
6 0: Edge trigger
1: Level trigger.
5-3 Reserved
2 Enables the generation of an SMI# due to WDT’s IRQ (EN_WDT).
1 Enables the generation of an SMI# due to CIR’s IRQ (EN_CIR).
0 Enables the generation of an SMI# due to PBD’s IRQ (EN_PBD).
8.11.20 SMI# Status Register 1 (Index=F2h, Default=00h)
This register is used to read the status of SMI# inputs.
Bit
7 MIDI’s IRQ
6 KBC (PS/2 Mouse)’s IRQ
5 KBC (Keyboard)’s IRQ
4 FAN Controller’s IRQ
3 Parallel Port’s IRQ
2 Serial Port 2’s IRQ
1 Serial Port 1’s IRQ
0 FDC’s IRQ
Description
8.11.21 SMI# Status Register 2 (Index=F3h, Default=00h)
This register is used to read the status of SMI# inputs.
Bit
7-3 Reserved
2 WDT’s IRQ
1 CIR’s IRQ
0 PBD’s IRQ
Description
8.11.22 SMI# Pin Mapping Register (Index=F4h, Default=00h)
Bit
Description
7-6 Reserved
5-0 SMI# Pin Location
Please see Location mapping table ^Note4.
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IT8702F V0.5