IT8702F Datasheet, PDF (138/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
(1) Data Port (Base Address 1 + 00h)
This is a bi-directional 8-bit data port. The direction of data flow is determined by the bit 5 of the logic state of
the control port register. It forwards directions when the bit is low and reverses directions when the bit is high.
(2) Status Port (Base Address 1 + 01h)
This is a read only register. Writing to this register has no effects. The contents of this register are latched
during an IOR cycle.
Bit 7 - BUSY#: Inverse of printer BUSY signal, a logic "0" means that the printer is busy and cannot accept
another character. A logic "1" means that it is ready to accept the next character.
Bit 6 - ACK#: Printer acknowledge, a logic "0" means that the printer has received a character and is ready to
accept another. A logic "1" means that it is still processing the last character.
Bit 5 - PE: Paper end, a logic "1" indicates the paper end.
Bit 4 - SLCT: Printer selected, a logic "1" means that the printer is on line.
Bit 3 - ERR#: Printer error signal, a logic "0" means an error has been detected.
Bits 2, 1 - Reserved: These bits are always "1" when read.
Bit 0 - TMOUT: This bit is valid only in EPP mode and indicates that a 10-msec time-out has occurred in EPP
operation. A logic "0" means no time-out occurred and a logic “1” means that a time-out error has been
detected. This bit is cleared by an LRESET# or by writing a logic “1” to it. When the IT8702F is selected to
non-EPP mode (SPP or ECP), this bit is always a logic "1" when read.
(3) Control Port (Base Address 1 + 02h)
This port provides all output signals to control the printer. The register can be read and written.
Bits 6, 7- Reserved: These two bits are always "1" when read.
Bit 5 - PDDIR: Data port direction control. This bit determines the direction of the data port register. Set this
bit "0" to output the data port to PD bus, and "1" to input from PD bus.
Bit 4 - IRQE: Interrupt request enable. Setting this bit "1" enables the interrupt requests from the parallel port
to the Host. An interrupt request is generated by a "0" to "1" transition of the ACK# signal.
Bit 3 - SLIN: Inverse of SLIN# pin. Setting this bit to "1" selects the printer.
Bit 2 - INIT: Initiate printer. Setting this bit to "0" initializes the printer.
Bit 1 - AFD: Inverse of the AFD# pin. Setting this bit to "1" causes the printer to automatically advance one
line after each line is printed.
Bit 0 - STB: Inverse of the STB# pin. This pin controls the data strobe signal to the printer.
(4) EPP Address Port (Base Address 1 + 03h)
The EPP Address Port is only available in the EPP mode. When the Host writes to this port, the contents of
D0 -D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active when LPC I/O
WRITE cycle is on this address) causes an EPP ADDRESS WRITE cycle. When the Host reads from this
port, the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active when LPC I/O
READ cycle is on this address) causes an EPP ADDRESS READ cycle.
(5) EPP Data Ports 0-3 (Base Address 1 + 04-07h)
The EPP Data Ports are only available in the EPP mode. When the Host writes to these ports, the contents of
D0 - D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active when LPC I/O
WRITE cycle is on this address) causes an EPP DATA WRITE cycle. When the Host reads from these ports,
the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active when LPC I/O READ
cycle is on this address) causes an EPP DATA READ cycle.
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IT8702F V0.5