IT8702F Datasheet, PDF (63/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

Configuration
8.7 Parallel Port Configuration Registers (LDN=03h)
8.7.1 Parallel Port Activate (Index=30h, Default=00h)
Bit
7-1 Reserved
0 Parallel Port Enable
1: Enabled
0: Disabled
Description
8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)
Bit
Description
7-4 Read only as “0h” for Base Address[15:12]
3-0 Read/write, mapped as Base Address[11:8]
8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)
If the bit 2 is set to 1, the EPP mode is disabled automatically.
Bit
Description
7-2 Read/write, mapped as Base Address[7:2]
1-0 Read only as “00b.”
8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)
Bit
Description
7-4 Read only as “0h” for Base Address[15:12]
3-0 Read/write, mapped as Base Address[11:8]
8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h)
Bit
Description
7-2 Read/write, mapped as Base Address[7:2]
1-0 Read only as “00b.”
8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h)
Bit
Description
7-4 Reserved with default “0h.”
3-0 Select the interrupt level ^Note1 for Parallel Port
8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h)
Bit
Description
7-3 Reserved with default “00h.”
2-0 Select the DMA channel ^Note2 for Parallel Port.
www.ite.com.tw
47
IT8702F V0.5