IT8702F Datasheet, PDF (142/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

IT8702F
(6) Device Status Register (dsr) (Base 1 +01h, Mode All)
Bits 0, 1 and 2 of this register are not implemented. These bit states are remained at high in a READ
operation of the Printer Status Register.
dsr(7): This bit is the inverted level of the Busy input.
dsr(6): This bit is the state of the nAck input.
dsr(5): This bit is the state of the PError input.
dsr(4): This bit is the state of the Select input.
dsr(3): This bit is the state of the nFault input.
dsr(2)-dsr(0): These bits are always 1.
(7) Device Control Register (dcr) (Base 1+02h, Mode All)
Bits 6 and 7 of this register have no function. They are set high during the READ operation, and cannot be
written. Contents in bits 0-5 are initialized to 0 when the RESET pin is active.
dcr(7)-dcr(6): These two bits are always high.
dcr(5):Except in the modes 000 and 010, setting this bit low means that the PD bus is in output operation;
setting it high, in input operation. This bit will be forced to low in mode 000.
dcr(4): Setting this bit high enables the interrupt request from peripheral to the host due to a rising edge
of the nAck input.
dcr(3): It is inverted and output to SelectIn.
dcr(2): It is output to nInit without inversion.
dcr(1): It is inverted and output to nAutoFd.
dcr(0): It is inverted and output to nStrobe.
(8) Parallel Port Data FIFO (cFifo) (Base 2+00h, Mode 010)
Bytes written or DMA transferred from the Host to this FIFO are sent by a hardware handshaking to the
peripheral according to the Standard Parallel Port protocol. This operation is only defined for the forward
direction.
(9) ECP Data FIFO (ecpDFifo) (Base 2+00h, Mode 011)
When the direction bit dcr(5) is 0, bytes written or DMA transferred from the Host to this FIFO are sent by
hardware handshaking to the peripheral according to the ECP parallel port protocol. When dcr(5) is 1, data
bytes from the peripheral to this FIFO are read in an automatic hardware handshaking. The Host can receive
these bytes by performing READ operations or DMA transfers from this FIFO.
(10) Test FIFO (tFifo) (Base 2+00h, Mode 110)
The host may operate READ/WRITE or DMA transfers to this FIFO in any directions. Data in this FIFO will be
displayed on the PD bus without using hardware protocol handshaking. The tFifo will not accept new data
after it is full. Making a READ from an empty tFifo causes the last data byte to return.
(11) Configuration Register A (cnfgA) (Base 2+00h, Mode 111)
This read only register indicates to the system that interrupts are ISA-Pulses compatible. This is an 8-bit
implementation by returning a 10h.
(12) Configuration Register B (cnfgB) (Base 2+01h, Mode 111)
This register is read only.
cnfgB(7): A logic “0” read indicates that the chip does not support hardware RLE compression.
cnfgB(6): Reserved.
cnfgB(5)-cnfg(3): A value 000 read indicates that the interrupt must be selected with jumpers.
cnfgB(2)-cnfg(0): A value 000 read indicates that the DMA channel is jumpered 8-bit DMA.
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IT8702F V0.5