IT8702F Datasheet, PDF (133/173 Pages) List of Unclassifed Manufacturers – Super-Low Pin Count Input/Output (LPC I/O)

Functional Description
9.8.4 Baud Rate Relationship Between UART and Smart Card Interface
To perform serial transfers correctly, the baud rate of UART must be set in ways similar to the ICC card.
• Formula (Variation < 2%)
UART
Smart Card
Baud Rate =
24 MHz
13
16 * N
≈
SCRCLK * D
F
N =Divisor of UART, assigned by programming the DLM (Divisor Latch MSB) and DLL (Divisor Latch LSB).
F =Clock Rate Conversion Factor, default = 372.
D =Bit Rate Adjustment Factor, Default is 1.
SCRCLK duty cycle is 45%-55%.
• ICC With Internal Clock
ICC may use built-in internal clock, then the Baud rate is 9600 baud, just programming the Divisor Latch
Registers of UART in the IT8702F for SCR IFD.
• ICC Without Internal Clock
Baud rate is SCRCLK/372 before negotiating, and SCRCLK is limited within 1 MHz - 5MHz. During the ATR
sequence, the default F value (Clock Rate Conversion Factor) is 372, and the default D value (Bit Rate
Adjustment Factor) is 1.
9.8.5 Waveform Relationship
9600 Baud
Rate Output
SCRIO
(24 MHz/13)/12
16 BAUD clocks
(24 MHz/13)/12/16
1/9600 seconds
SCRCLK
1 etu=372 SCRCLK
9.8.6 Clock Divider
Figure 9-5. 9600 Baud Rate Example
The SCRCLK is generated as the selection of SCR_CLKSEL1-0, which are determined in the S1 Special
Configuration register 3 (LDN1_F2h) or S2 Special Configuration register 3 (LDN2_F2h).
Table 9-37. SCRCLK Selections
SCR_CLKSEL1-0
Selections
00
Stop
01
3.5 MHz
10
7.1 MHz
11
96 MHz / SCR DIV96M ^Note
Note: SCR DIV96M is determined by S1 Special Configuration Register 4
(LDN1_F3h) or S2 Special Configuration Register 4 (LDN2_F3h).
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