PT7A4401C Datasheet, PDF (6/27 Pages) List of Unclassifed Manufacturers – PT7A4401C T1/E1 System Synchronizer

Data Sheet
PT7A4401C T1/E1 System Synchronizer
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Functional Description
The DCO synchronization method depends upon the
PT7A4401C operating state, as follows:
Overall Operation
The PT7A4401C is a multitrunk synchronizer that provides
the clock and frame signals for T1 and E1 primary rate digital
transmission links.
It basically consists of the Master Clock Circuit, Digital Phase-
Locked Loop (DPLL), Input Impairment Monitor and Output
Circuit.
In Normal state, each DCO generates an output signal which is
frequency and phase locked to the input reference signal.
In Auto-Holdover state, each DCO generates an output signal
whose frequency is equal to what it was for a 30ms period
shortly before the end of the last Normal State.
In Free-Run state, the DCOs are free running with an accuracy
equal to the accuracy of the OSCi 20MHz source.
The DPLL circuit is employed to provide synchronization of
the output signals.
Referring to the block diagram on Page 3, the detailed func-
tions of the PT7A4401C are described as follows.
Master Clock
As its master clock, the PT7A4401C uses either an external
clock source or an external crystal and a few discrete compo-
nents with its internal oscillator.
Major Digital Phase-Locked Loop (DPLL) Block
The major DPLL blocks are the Phase Detector, Limiter, Loop
Filter, and Digitally Controlled Oscillators (DCO1 and DCO2).
The input signal is sent to the Phase Detector for comparison
with the feedback Signal from the Feedback Frequency Select
MUX. An error signal corresponding to their instantaneous
phase difference is produced and sent to the Limiter.
The Limiter amplifies this error signal to ensure that the DPLL
responds to all input transient conditions with a maximum
output phase slope of 5ns per 125µs. This performance easily
meets the maximum phase slope of 7.6ns per 125µs or 81ns per
1.326ms specified by AT&T TR62411.
The Loop Filter is a 1.9Hz low pass filter for all three reference
frequency selections: 8kHz, 1.544MHz and 2.048MHz. This
filter ensures that the jitter transfer requirements in ETS 300-
011 and AT&T TR62411 are met.
Output Circuit
Signals from the two DCOs are sent to the Output Circuit to
generate two clock signals, 12.352MHz and 16.384MHz,
which are divided in the T1 and E1 Dividers respectively to
provide needed clock and frame signals.
The T1 Divider uses the 12.352MHz signal to generate two
clock signals, C1.5 and C3. They have a nominal 50% duty
cycle.
The E1 Divider uses the 16.384MHz signal to generate four
clock signals and three frame signals, i.e., C2, C4, C8, C16,
F0, F8 and F16. The frame signals are generated directly from
the C16 signal.
The C2, C4 and C8 signals have a nominal 50% duty cycle,
and C16’s duty cycle is about 50% if the master clock has a
50% duty cycle.
All the frame and clock outputs are locked to each other for all
operating states. They have limited driving capability and
should be buffered when driving high capacitance loads.
Feedback Frequency Selection MUX
The feedback frequency is selected by FS1 and FS2 (as shown
in Table 3) to match the particular incoming reference fre-
quency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must
be performed after every frequency select input change.
Input Impairment Monitor
The Error Signal, after being limited and filtered, is sent to two
Digitally Controlled variable frequency Oscillators (DCO1 and
DCO2). Based upon the processed error value, the DCOs will
generate the corresponding digital output signals to the Out-
put Circuit to produce 12.352MHz and 16.384MHz signals.
This circuit monitors the input signal to the DPLL and auto-
matically enables Auto-Holdover state when the incoming sig-
nal is completely lost, or if its frequency is outside the Auto-
holdover capture range (either a small or large amount). When
the incoming signal returns to normal, the DPLL will be re-
turned to Normal State.
PT0108(09/02)
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