PT7A4401C Datasheet, PDF (24/27 Pages) List of Unclassifed Manufacturers – PT7A4401C T1/E1 System Synchronizer

Data Sheet
PT7A4401C T1/E1 System Synchronizer
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Notes:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Supply voltage and operation temperature are as per Recommended Operating Conditions.
3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
Test Conditions:
1. Normal State selected.
2. Auto-Holdover State.
3. Freerun State selected.
4. 8kHz frequency source selected.
5. 1.544MHz frequency source selected.
6. 2.048MHz frequency source selected.
7. Master clock input OSCi at 20MHz ±0ppm.
8. Master clock input OSCi at 20MHz ±32ppm.
9. Master clock input OSCi at 20MHz ±100ppm.
10. Reference input at ±0ppm.
11. Reference input at ±32ppm.
12. Reference input at ±100ppm.
13. For Freerun State of ±0ppm.
14. For Freerun State of ±32ppm.
15. For Freerun State of ±100ppm.
16. For capture range of ±230ppm.
17. For capture range of ±198ppm.
18. For capture range of ±130ppm.
19. 25pF capacitive load.
20. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI
p-p where 1UI p-p = 1/20MHz.
21. Jitter on reference input is less than 7ns p-p.
22. Applied jitter is sinusoidal.
23. Minimum applied input jitter magnitude to regain syn-
chronization.
24. Loss of synchronization is obtained at slightly higher in-
put jitter amplitudes.
25. Within 10 ms of the state or input change
26. 1UIpp = 125µs for 8kHz signals.
27. 1UIpp = 648ns for 1.544MHz signals.
28. 1UIpp = 488ns for 2.048MHz signals.
29. 1UIpp = 323ns for 3.088MHz signals.
30. 1UIpp = 244ns for 4.096MHz signals.
31. 1UIpp = 122ns for 8.192MHz signals.
32. 1UIpp = 61ns for 16.384MHz signals.
33. No filter.
34. 40Hz to 100kHz bandpass filter.
35. With respect to reference input signal frequency.
36. After a RST.
37. Master clock duty cycle 40% to 60%.
38. Prior to Auto-Holdover State, device was in Normal State
and phase-locked.
PT0108(09/02)
24
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