PT7A4401C Datasheet, PDF(10/27 Page) List of Unclassifed Manufacturers

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Data Sheet

PT7A4401C T1/E1 System Synchronizer

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Detailed Specifications

Definitions of Critical Performance Specifications

Intrinsic Jitter: Intrinsic jitter is the jitter produced by the

synchronizing circuit. It is measured by applying a reference

signal with no jitter to the input of the device, and measuring

its output jitter. Intrinsic jitter may also be measured when the

device is in a non-synchronizing mode--such as free running

or auto-holdover--by measuring the output jitter of the device.

Intrinsic jitter is usually measured with various band limiting

filters depending on the applicable standards.

Jitter Tolerance: Jitter tolerance is a measure of the ability of

a PLL to operate properly (i.e., remain in lock and/or regain

lock in the presence of large jitter magnitudes at various jitter

frequencies) when jitter is present on its reference. The appli-

cable standard specifies how much jitter to apply to the refer-

ence when testing for jitter tolerance.

Jitter Transfer: Jitter transfer or jitter attenuation refers to the

magnitude of jitter at the output of a device with respect to a

given amount of jitter at the input of the device. Input jitter is

applied at various amplitudes and frequencies, and output jit-

ter is measured with various filters depending on the appli-

cable standard.

Its 3 possible input frequencies and 9 outputs gives the

PT7A4401C 27 possible jitter transfer combinations. How-

ever, only three cases of the jitter transfer specifications are

given in the AC Electrical Characteristics; as the remaining

combinations can be derived from them.

For the PT7A4401C, jitter attenuation is determined by the

internal 1.9Hz low pass loop filter and phase slope limiter. The

phase slope limiter limits the output phase slope to 5ns/125Âµs.

Therefore, if the input signal exceeds this rate, such as for very

large amplitude low frequency input jitter, the maximum out-

put phase slope will be limited (i.e., attenuated) to 5ns/125Âµs.

It should be noted that 1UI at 1.544MHz (644ns) is not equal

to 1UI at 2.048MHz (488ns). A transfer value using different

input and output frequencies must be calculated in common

units (e.g., seconds) as shown in the following example.

Example - When the T1 input jitter is 20UI (T1 UI Units) and

the T1 to T1 jitter attenuation is 18dB, the T1 and E1 output

jitter can be calculated as follows:

JT1o

JT1i

10 (

-A

10 (

-18

2.5UI

J = J x ( 1UIT1) = J x ( 644ns ) = 3.3UI

E1o T1o

T1o

1UIE1

488ns

Using the above method, the jitter attenuation can be calcu-

lated for all combinations of inputs and outputs based upon

the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combina-

tions of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs

(8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz,

16.384MHz) for a given input signal (jitter frequency and jit-

ter amplitude) are the same.

As intrinsic jitter is always present, jitter attenuation will ap-

pear to be lower for small input jitter signals than for large

ones. Consequently, accurate jitter transfer function measure-

ments are usually made with large input jitter signals (e.g.,

75% of the specified maximum jitter tolerance).

Frequency Accuracy: Frequency accuracy is defined as the ab-

solute tolerance of an output clock signal when it is operating in

a free running mode (not locked to an external reference). For the

PT7A4401C, Free-Run accuracy is equal to the Master Clock

(OSCi) accuracy.

Auto-Holdover Accuracy: Auto-Holdover accuracy is defined as

the absolute tolerance of an output clock signal, when it is not

locked to an external reference signal, but is operating using

storage techniques. For the PT7A4401C the storage value is deter-

mined while the device is in Normal State and locked to an exter-

nal reference signal. The absolute Master Clock (OSCi) accuracy

of the PT7A4401C does not affect Auto-Holdover accuracy, but

the change in OSCi accuracy while in Auto-Holdover State does.

Lock Range: If the PT7A4401C DPLL is already in a state of

synchronization (âlockâ) with the incoming reference signal,

it is able to track this signal to maintain lock as its frequency

varies over a certain range, called the Lock Range. The size of

Lock Range is related to the range of the Digitally Controlled

Oscillators and is equal to 230ppm minus the accuracy of the

master clock (OSCi). For example, a 32ppm master clock re-

sults in a Lock Range of 198ppm.

Capture Range: If the PT7A4401C DPLL is not at present in a state

of synchronization (lock) with the incoming reference signal, it is

able to initiate (acquire) lock only if the signalâs frequency is

within a certain range, called the Capture Range. For any PLL, no

portion of the Capture Range can fall outside the Lock Range,

and, in general, the Capture Range is more narrow than the Lock

Range. However, owing to the design of its Phase Detector, the

PT7A4401Câs Capture Range is equal to its Lock Range.

Phase Slope: Phase slope is measured in seconds per second

and is defined as the rate at which a given signal changes

phase with respect to an ideal signal of constant frequency.

The given signal is typically the output signal. The ideal sig-

nal has a constant frequency that is nominally equal in value

to that of the final output signal or final input signal.

PT0108(09/02)

Ver:0

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