PT7A4401C Datasheet, PDF (5/27 Pages) List of Unclassifed Manufacturers – PT7A4401C T1/E1 System Synchronizer

Data Sheet
PT7A4401C T1/E1 System Synchronizer
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Pin Description
Table 2. Pin Description
Pin
Name
Type
Descr iption
1, 15
2, 3, 19, 21,
22, 24, 25
4
GND
NU
REF
Ground Ground (0V)
I Not Used (should be connected to ground)
I Reference Input (TTL compatible): Input reference signals
5, 18
6
V_cc
OSCo
Power Power Supply (+5V)
O Oscillator Master Clock Output (CMOS): Output of 20MHz master clock
7
OSCi
I
Oscillator Master Clock Input (CMOS): Input of 20MHz master clock (can be
connected directly to a clock source)
Fr ame Pulse Output (CMOS Compatible): 8kHz framing output pulse that indicates
8
F16
O the start of the ST-BUS frame. The pulse width is based upon the period of the
16.384MHz synchronization clock.
Fr ame Pulse Output (CMOS Compatible): 8kHz output framing pulse that indicates
9
F0
O the start of the active ST-BUS frame. The pulse width is based upon the period of the
4.096MHz synchronization clock.
Fr ame Pulse Output (CMOS Compatible): 8kHz output framing pulse that indicates
10
F8
O the start of the active ST-BUS frame. The pulse width is based upon the period of the
8.192MHz synchronization clock.
11
C1.5
O 1.544MHz Clock (CMOS Compatible)
12
C3
O 3.088MHz Clock (CMOS Compatible)
13
C2
O 2.048MHz Clock (CMOS Compatible)
14
C4
O 4.096MHz Clock (CMOS Compatible)
16
C8
O 8.192MHz Clock (CMOS Compatible)
17
C16
O 16.384MHz Clock (CMOS Compatible)
20
NC
O Not Connected: Make no connection to this pin.
23
MS
I
Mode Select (TTL Compatible): This input selects the operation mode of the device,
i.e., Normal or Freerun. Refer to Table 4.
Frequency Select 2 (TTL Compatible): This input, together with FS1, selects the
26
FS2
I frequency of the input reference signal, either 8kHz, 1.544MHz or 2.048MHz. Refer to
Table 3.
27
FS1
I Frequency Select 1 (TTL Compatible): Refer to the pin description of FS2.
Reset (CMOS Input Schmitt Tr igger ): Reset the device when at low level. The reset
is needed when power-up or when frequency select input change to ensure proper
28
RST
I operation. The time constant for a power-up reset circuit must be a min. of five times the
rise time of the power supply. In normal operation, the RST pin must be held low for a
min. of 300 ns to reset the device. When RST at low level, all outputs are fixed at HIGH.
PT0108(09/02)
5
Ver:0