OXFW900-TQ-A Datasheet, PDF (6/30 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
OXFW900
56
I CKIN
23
IU RESET#
113
T_O CKOUT
123
IU FORCE#
124, 125
IU TEST[1:0]
Power and ground²
28, 47, 94, 114
17, 24, 59, 84, 88, 121
3V3 3.3V AC VDD
3V3 3.3V DC VDD
9, 38, 76, 112
5V 5V BIAS VDD
8, 27, 46, 67, 75, 93, 106
G AC GND
16, 22, 39, 55, 68, 83, 87, 107, 119 G DC GND
Direct clock input. Used in conjunction with an external
crystal oscillator of 24.576MHz. If a crystal is connected to
XTLI and XTLO this input must be tied low for the OXFW900
to operate. Mark space ratio of crystal oscillator must be
45:55 or better. IMPORTANT – Please refer to Application
Notes regarding clocking
Global reset for the OXFW900. Active Low.
Clock output. 24.576 MHz clock output. IMPORTANT –
Please refer to Application Notes regarding clocking
This input is used to allow the OXFW900 to reprogram a
flash which has been loaded with a bad program. A bad
program is defined as one that does not have the correct
interlocking mechanism for reprogramming flash. This pin
forces the ARM watchdog timer to trigger thus allowing the
flash to be reprogrammed over the 1394 bus as if the flash
were blank.
‘11’ = NORMAL OPERATION. These pins have internal
pullup resistors and must be left unconnected. Other settings
are for foundry test purposes only.
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies 5V reference bias to all 5V tolerant I/O. All four
MUST be connected to 5V rail.
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
Table 1: Pin Descriptions
Note 1: Direction key:
I
Input
IU
Input with internal pull-up
ID
Input with external pull-down
O
Output
I/O Bi-directional
T_I 5V tolerant input
T_O 5V tolerant output
T_I/O 5V tolerant bi-directional
G
Ground
3V3 3.3V power
5V
5V bias power
Note 2: Power & Ground
There are two GND and three VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail). A
third rail provides 5V bias voltage to 5V tolerant IO.
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip.
Data Sheet Revision 1.0
Page 6