OXFW900-TQ-A Datasheet, PDF (12/30 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
OXFW900
6.3 External Processor Interface
Name
tas
tcss
tws
taddr1
taddr2
tiorl
tah
tdsa
tdha
tdsb
tdhb
dsa1
dha1
dsb1
dhb1
dsa2
dha2
dsb2
dhb2
tahr
tasr
tiorh
tds
tdh
tcsh
tcsa
twel
tah
tas1
tah1
tas2
tah2
tweh
Description
Common Timings
Address valid to CSx# and OE# falling
CSx# and OE# falling to WE# or IOR# falling
Wait State Additional Delay
Not Last Address Valid
Last Address Valid
Common Read Timings
IOR# valid
Address hold after CSx# or OE# rising
Single Access Read Timings
Data valid and stable to CSx# and OE# rising
Data hold after CSx# and OE# rising
Data valid and stable to IOR# rising
Data hold after IOR# rising
Multiple Access Read Timings
Data valid and stable to CSx# and OE# rising (not last access)
Data hold after CSx# and OE# rising (not last access)
Data valid and stable to IOR# rising (not last access)
Data hold after IOR# rising (not last access)
Data valid and stable to CSx# and OE# rising (last access)
Data hold after CSx# and OE# rising (last access)
Data valid and stable to IOR# rising (last access)
Data hold after IOR# rising (last access)
IOR# rising to next address valid
Address valid to IOR# falling
IOR# inactive between reads
Common Write Timings
Data valid to WE# rising
Data hold after WE# rising
CS# hold after WE# rising
CS# hold after Address invalid
WE# valid
Single Access Write Timings
Address hold after WE# rising
Multiple Access Write Timings
Address valid to CSx# and OE# falling
Address hold after WE# rising (not last access)
WE# falling after next address valid
Address hold after WE# rising (last access)
WE# inactive between writes
min (ns)
-
0.3
16
0
typ (ns)
-
0
max (ns)
-
2.5
18.5
600
-
-
-
-
-
-
0
0
-
-
-
0
0
0
0
-
-
-
39+tws
13
17
20
1
2.5
-
-
-
19
60
-
-
-
Table 9: External Processor Interface timings
All timings are preliminary and are subject to change
Data Sheet Revision 1.0
Page 12