OXFW900-TQ-A Datasheet, PDF (11/30 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
6.2 1394 Link-Phy interface
The timings for 1394 Link – Phy are shown below :
Symbol Parameter
Min
tlsu Setup Time, PD[7:0] and CTL[1:0] before PhyClk
6
tlh Hold Time, PD[7:0] and CTL[1:0] after PhyClk
0
Tld1 Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0]
TBD
and Lreq outputs valid
Tld2 Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0],
TBD
CTL[1:0] and Lreq outputs valid
Tld3 Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs
TBD
invalid (high impedance)
Table 8: OXFW900 Link-Phy interface timings
OXFW900
Max
Units
ns
ns
TBD
ns
TBD
ns
TBD
ns
Data Sheet Revision 1.0
Page 11