56F8357 Datasheet, PDF (51/172 Pages) List of Unclassifed Manufacturers – 16-BIT HYBRID CONTROLLERS

Peripheral Memory Mapped Registers
Table 4-10 External Memory Integration Registers Address Map (Continued)
(EMI_BASE = $00 F020)
Register Acronym
CSOR 6
CSOR 7
CSTC 0
CSTC 1
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
Address Offset
Register Description
$E
Chip Select Option Register 6
$F
Chip Select Option Register 7
$10
Chip Select Timing Control Register 0
$11
Chip Select Timing Control Register 1
$12
Chip Select Timing Control Register 2
$13
Chip Select Timing Control Register 3
$14
Chip Select Timing Control Register 4
$15
Chip Select Timing Control Register 5
$16
Chip Select Timing Control Register 6
$17
Chip Select Timing Control Register 7
$18
Bus Control Register
Reset Value
0x016B sets the default number of
wait states to 11 for both read and
write accesses
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym Address Offset
Register Description
TMRA0_CMP1
TMRA0_CMP2
TMRA0_CAP
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCR
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
TMRA1_LOAD
TMRA1_HOLD
$0
Compare Register 1
$1
Compare Register 2
$2
Capture Register
$3
Load Register
$4
Hold Register
$5
Counter Register
$6
Control Register
$7
Status and Control Register
$8
Comparator Load Register 1
$9
Comparator Load Register 2
$A
Comparator Status and Control Register
Reserved
$10
Compare Register 1
$11
Compare Register 2
$12
Capture Register
$13
Load Register
$14
Hold Register
56F8357 Technical Data, Rev. 8.0
Freescale Semiconductor
51
Preliminary