56F8357 Datasheet, PDF (19/172 Pages) List of Unclassifed Manufacturers – 16-BIT HYBRID CONTROLLERS

Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
V_{SSA_ADC}
OCR_DIS
115
Supply
91
Input
Input
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
On-Chip Regulator Disable —
Tie this pin to V_SS to enable the on-chip regulator
Tie this pin to V_DD to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
V_CAP1*
V_CAP2*
V_CAP3*
V_CAP4*
62
Supply
Supply V_CAP1 - 4 — When OCR_DIS is tied to V_SS (regulator enabled),
connect each pin to a 2.2µF or greater bypass capacitor in order to
144
bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to V_DD (regulator disabled),
95
these pins become V_{DD_CORE} and should be connected to a
15
regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
* When the on-chip regulator is disabled, these four pins become 2.5V V_{DD_CORE}.
V_PP1
V_PP2
141
Input
2
Input
V_PP1 - 2 — These pins should be left unconnected as an open
circuit for normal functionality.
CLKMODE
99
Input
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
EXTAL
XTAL
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
94
Input
Input
External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by an
external clock source.
93
Input/ Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
56F8357 Technical Data, Rev. 8.0
Freescale Semiconductor
19
Preliminary