NT68P62-01 Datasheet, PDF (43/56 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K OTP ROM Type)

NT68P62-01
15.4 DDC2B+ Master Mode Bus Interface
Most of the DDC manipulation is the same as SLAVE mode
except the SCL clock generation. In the MASTER mode,
the control of SCL clock source belongs to NT68P62. Users
must set the calling address and transmission direction in
advance. Access the
transmission flow of
communication.
&
bits to control the
DDC2B+ master mode
Start condition: After user clearing
&
bit,
the system will generate a 'START' condition on the SCL &
SDA lines and wait for user to put the calling address into
TXDAT buffer and send to SDA line. The frequency of SCL
is dependant on the baud-rate setting value (DDCBR0 -
DDCBR2) in register CH0CLK. And the data transmission
direction will be dependant on the
bit and the LSB of
calling address, '1' for read operation and '0' for write
operation.
Calling address: Calling address is 8 bits long. It should be
put in the CH0TXDAT. The setting of LSB bit in this TXDAT
buffer should be as same as
bit.
STOP condition: There are several cases that the system
will send out 'STOP' condition on the SCL & SDA lines.
First, in the 'READ' operation, if user sets TXACK bit to '1',
the system will send out 'NAK' condition on the bus after
receiving one byte data and then send out 'STOP' condition
automatically later. Second, in the 'START' condition and
after sending out calling address, if no slave has respond to
a 'ACK' signal, the master will send out 'STOP' condition
automatically. Third, if user sets
bit to '1', the
system will generate a 'STOP' condition after the current
byte transmission is done. Notice that if slave device did
not released SCL and SDA line, the system can not send
out 'STOP' condition.
After 'STOP' condition, the master will release SCL & SDA
lines and return to SLAVE mode.
The INTTX0 & INTRX0 interrupt: After NT68P62
completing one byte transmission or receiving, it will
generate an INTTX0 (WRITE mode) & INTRX0 (READ
mode) interrupts. Users can control the flow of DDC2B
transmission at these interrupts.
The INTRX0 on the read mode: NT68P62 reads data from
external slave device. When users detect a INTRX0
interrupt, it means there is one byte data received and user
can read out by accessing CH0RXDAT control register. At
the same time, if the user responded an 'ACK' signal
beforehand, the shift register will send out an 'ACK' bit (low
voltage) and continue to receive next byte data. If both the
shift register and CH0RXDAT register are full and user still
did not load data from CH0RXDAT register, the SCL will be
held LOW and wait for NT68P62. After user has received
one byte data from CH0RXDAT register, the SCL will be
released for generation of SCL transmission clock. An
external device can continue sending next byte data to
NT68P62. Refer Figure 15.7 for the timing diagram. User
must respond to a NAK signal in advance to stop the
transmission. Before the last two bytes of data is received,
user should respond an 'NAK' signal. Then, system will
send out 'NAK' bit after receiving the last byte data and
'STOP' condition to notify the slave terminated current
transmission.
The INTTX0 on the WRITE mode: External device read
data from NT68P62. At INTTX0 interrupt, the system will
load new data from CH0TXDAT register which has been
put by user beforehand into internal shift register and
continue sending out this new data. After this new loading
data be shifted out according every SCL clock, system will
request user to put next byte data into CH0TXDAT register.
If both of shift register and CH0TXDAT register are empty
and user still not load data to CH0TXDAT register, the SCL
will be held LOW and wait for NT68P62 after receiving the
acknowledgment bit.
If SCL is held low by system, and user has put one new
byte data into CH0TXDAT register, the SCL will be
released for generation of SCL transmission clock. At this
time, system will load this byte data into shift register and
generate an INTTX0 interrupt again to remind user putting
next byte into CH0TXDAT register. Refer to Figure 15.8 for
the timing diagram.
Repeat start condition: If clearing the
bit to '0' in
the ' WRITE' operation, system will send out a R' EPEAT
START'. Notice that if slave device did not release SCL and
SDA line, the system can not send out 'REPEAT START
condition.
SCL baud rate selection: There are three Baud Rate bits for
user to select one of eight clock rates on the SCL line. After
system reset, the default value of these Baud Rate bits
(DDC2BR0-2) are '111'.
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