NT68P62-01 Datasheet, PDF (18/56 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K OTP ROM Type)

NT68P62-01
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt
INTS INT
INTA INT
INTTX INT
INTRX INT
INTNAK INT
INTSTOP INT
Meaning
SCL Go-Low INT
Address Matched
INT
Transfer Buffer
Empty INT
Receiving Buffer
Overflow INT
No Acknowledge
INT
DDC2 Stop INT
Action
In DDC1 mode, it will be activated when the external device proceed a DDC2
communication. This action includes pull the SCL line to ground or send out an
'START' condition directly. System will respond to this action by changing
DDC1 mode to DDC2 slave mode.
It will be activated at DDC2 slave mode when the external device call NT68P62
slave address. If this calling address matches the NT68P62 address, system
will generate this interrupt to remind user
It will be activated at DDC2 mode when transmission buffer, IIC_TXDAT, is
empty at transmission mode.
It will be activated at DDC2 mode when new data have store in the
IIC_RXDAT register at receive mode.
At transmission mode, this interrupt will be activated when NT68P62 have
send out one byte data but the external device does not respond an
acknowledge bit to it.
In SLAVE mode, this interrupt will be activated when the NT68P62 receives an
'STOP' condition.
IRQ0
INTSTOP0
INTNAK0
INTRX0
INTTX0
INTA0
INTS0
IRQ1
INTSTOP1
INTNAK1
INTRX1
INTTX1
INTA1
INTS1
IRQ2
INTMR
INTE1
INTV
INTADC
NMIPOLL
INTMUTE
INTE0
IEIRQ0
IEIRQ1
IEIRQ2
IENMI
IRQ0
IRQ1
IRQ (to CPU 6502)
IRQ2
NMI (to CPU 6502)
Figure 11.1. Interrupt Controller Structure
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