NT68P62-01 Datasheet, PDF (41/56 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K OTP ROM Type)

NT68P62-01
Data transfer and wait: The data on the SDA line must be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. In the wired-AND connection, any slower
device can hold the SCL line LOW to force the faster
device into a wait state. Data transmition will be suspended
until the slower device is ready for the next byte transfer by
releasing the SCL line.
Acknowledge: The acknowledgment will be generated at
ninth clock by whom receiving data. In the WRITE MODE,
NT68P62 system must respond to this acknowledgment.
Users should clear the
bit in the CH0CON to open
the ‘ACK’ function. After receiving one byte data from
external device, NT68P62 will automatically send this
acknowledgment bit.
In the READ mode, an external device must respond to the
acknowledgment bit after every byte data is sent out. The
system will set the INTNAK bit when external device does
not send out the '0' acknowledgment bit. Furthermore, user
can open this interrupt source by clearing the INTNAK bit in
the IEIRQ0 register.
The INTTX0 & INTRX0 interrupt: After NT68P62 complete
one byte transmission or receiving, it will generate an
INTTX0 (READ mode) & INTRX0 (WRITE mode) interrupts.
These interrupts are generated at the falling edge of the
ninth clock. Users can control the flow of DDC2B
transmission at these interrupts.
The INTRX0 on the WRITE mode: NT68P62 read data
from external master device. When users detect an
INTRX0 interrupt, it means there has one byte data
received and user can read out by accessing CH0RXDAT
control register. At the same time, if user responded an
'ACK' signal beforehand, the shift register will send out this
'ACK' bit (low voltage) and continue to receive the next byte
data. If both of shift register and CH0RXDAT register are
full and user still did not load data from CH0RXDAT
register, the SCL will be held LOW and waiting for
NT68P62. After user obtains one byte data from
CH0RXDAT register, the SCL will be released for
generation of SCL transmission clock. External device can
continue sending next byte data to NT68P62. The timing
diagram refers to Figure 15.3. User must responde a NAK
signal in advance to stop the transmission.
The INTTX0 on the READ mode: External device read data
from NT68P62. At INTTX0 interrupt, the system will load
new data from CH0TXDAT register which has been put by
user beforehand into internal shift register and continue
sending out this new data. After this new loading data be
shifted out according every SCL clock, system will request
user to put next byte data into CH0TXDAT register.
If both of shift register and CH0TXDAT register are empty
and user still not load data to CH0TXDAT register, the SCL
will be held LOW and waiting by NT68P62 after receiving
the acknowledgment bit.
At SCL holded low by system, after user has put one new
byte data into CH0TXDAT register, the SCL will be
released for generation of SCL transmission clock. At this
time, system will load this byte data into shift register and
generate a INTTX0 interrupt again to remind user putting
next byte into CH0TXDAT register. The timing diagram
refer to Figure 15.4.
After every one byte data transfer, system will monitor if
external master device has sent out this acknowledgment
bit or not. If not, system will set the INTNAK bit (the
acknowledgment is LOW signal). Users will get a INTNAK
interrupt if INTNAK has been enabled as a interrupt source.
STOP condition: When SCL & SDA line have been
released (hold on 'high' state), DDC2B data transfer is
always terminated by a STOP condition generated by
external device. A STOP signal is defined as a LOW to
HIGH transition of SDA while SCL is at HIGH state. When
there is a STOP condition, NT68P62 will set the 'STOP' bit
& INTSTOP bit to '1' and user can poll this status bit or
open a INTSTOP interrupt to control DDC2B transmission
at any time. This bit will keep '1' until user clears it by
writing '1' to this bit. Notice the SCL and SDA lines must
conform to I²C bus specifications. For the software
flowchart can please refer Figure 15.6. Please refer to the
standard I²C bus specification for details.
Change to DDC1 mode: After an external device terminates
DDC2 transmission by sending a STOP condition, users
can set MD1/ to '1' for changing to DDC1 mode. On the
other hand, when the SCL line has been released (pulled-
up), user can force NT68P62 to DDC1 mode
communication at any time.
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