NT68P62-01 Datasheet, PDF (16/56 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K OTP ROM Type)

NT68P62-01
PWM DACs (continued)
DAC0 & DAC1 are shared with ADC2 & ADC3 input pins respectively. If ENADC2/3 bit in the ENADC control register is
cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC2/3 bits will be in HIGH state
and DAC0 & DAC1 will act as PWM output pins.
DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the ENDDC bit in the CH1CON control
register to LOW, channel 1 of DDC will be activated. When used as DDC channel, the I/O port will be an open drain structure
and include 'Schmitt Trigger' buffer for noise immunity. After the chip is reset, ENDDC bits will be in HIGH state and DAC4 -
DAC5 will act as PWM output pins.
Addr.
$000F
Register
ENDAC
$0010 ENADC
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
DACH0
DACH1
DACH2
DACH3
DACH4
DACH5
DACH6
DACH7
DACH8
DACH9
DACH10
DACH11
DACH12
INIT Bit7
Bit6
Bit5
Bit4
FFH
-
-
ENDK12 ENDK11
FFH _CSTA
-
-
-
80H DKVL7 DKVL6 DKVL5 DKVL4
80H DKVL7 DKVL6
80H DKVL7 DKVL6
DKVL5
DKVL5
DKVL4
DKVL4
80H DKVL7 DKVL6 DKVL5 DKVL4
80H DKVL7 DKVL6
80H DKVL7 DKVL6
DKVL5
DKVL5
DKVL4
DKVL4
80H DKVL7 DKVL6
-
-
-
DKVL5
-
DKVL4
-
80H DKVL7 DKVL6 DKVL5 DKVL4
80H DKVL7 DKVL6
80H DKVL7 DKVL6
DKVL5
DKVL5
DKVL4
DKVL4
80H DKVL7 DKVL6
80H DKVL7 DKVL6
DKVL5
DKVL5
DKVL4
DKVL4
80H DKVL7 DKVL6 DKVL5 DKVL4
Bit3
Bit2
Bit1
Bit0
R/W
ENDK10 ENDK9
ENDK8 _ENDK7 ^W
ENADC3 ENADC2 ENADC1 ENADC0 ^W
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
-
-
-
-
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DKVL3 DKVL2 DKVL1 DKVL0 RW
DAC control register ($000F) and DAC value register ($0030 - $003D)
16