NT68P62-01 Datasheet, PDF (29/56 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K OTP ROM Type)

NT68P62-01
13.2. Sync Processor Control Register:
Polarity: The detection of Hsync or Vsync polarity is
achieved by hardware circuit that samples the sync signal's
voltage level periodically. Users can read HPOLI & VPOLI
bit from HVCON register, which bit = '1' represents positive
polarity and '0' represents negative polarity. Furthermore,
users can read HSYNCI and VSYNCI bit in HVCON
register to detect H & V sync input signal. Users can control
the polarity of H & V sync output signal by writing the
appropriate data to the HPOLO and VPOLO bits in the
HVCON register, '1' represents positive polarity and '0',
negative polarity.
Composite sync: Users have to determine whether the
incoming signal is separate sync or composite sync and set
S/ C & ENHSEL / HSEL bit properly. If the input sync
signal is composite, after set S/ C to '0', the sync separator
block will be activated (please refer Figure 13.5). At the
area of Vsync pulse, there can exist Hsync pulses or not.
For the output of Hsync, users can active hardware to
interpolate the Hsync pulses in that area by clearing the
INSEN bit. The width of these inserted pulses is 2uS fixed
and the time interval is the same as previous one.
According to the last Hsync pulse outside the Vsync pulse
duration, the hardware will arrange the interval of these
hardware interpolated pulses. These inserted Hsync pulse
have 125 nS phase deviation maximum. The Vsync pulse
can be extracted by hardware from composite Hsync
signal, and the delay time of output Vsync signal will be
limited bellow 20ns. For inserting Hsync pulse safely, the
extracted Vsync pulse will be widens about 9µs. Because
evenly inserting the Hsync pulse, the last inserted Hsync
pulse will have different frequency from original ones.
System will not implement this insertion function, users
must clear INSEN bit in the SYNCON control register to
activate this function. After reset, S/ C & INSEN bits
default value is HIGH and clear the VCNT | HCNT counter
latches to zero.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output which are shared with P06
& P07 respectively. If ENVOUT & ENHOUT is set to '0' in
HVCON register, P06 & P07 will act as VSYNCO &
HSYNCO output pins. When the input sync is separate
signal, the V/HSYNCO will output the same signal as input
without delay. But if the input sync is composite signal, the
VSYNCO signal will have fixed delay time about 20ns and
the HSYNCO has nonfixed delay time about 125ns.
Half frequency Input and output: In pin assignment, when
users set ENHALF bits to '0' in HALFCON register, the
HALFHO pin will act as output pin and output half of input
signal in the HALFHI pin with 50% duty (see Figure 13.7). If
set NOHALF to '0', HALFHO will output the same signal in
the HALFHI pin and user can control its polarity of output
HALFHO by setting HALFPOL bit, '1' for positive and '0' for
negative polarity. After the chip is reset, ENHALF
NOHALF & HALFPOL will be in the HIGH state and P12 &
P13 will act as I/O pins. It is recommended to add a Schmitt
Trigger buffer at front of the HALFI pin.
Free run signal output: User can select one of free running
frequency (list bellow) outputting to HYSNCO & VSYNCO
pin by setting the FREQ0/1/2 bits. If user does not enable
H/VSYNCO by clearing ENVOUT or ENHOUT bits, any
setting of FREQ0/1/2 bits will be invalid. After system
reset, NT68P62 does not provide free running frequency
and both of FREQ0/1/2 bits are set to ' 1'. The free running
frequency can be set according the table below:
Free Running Freq.
1
2
3
4
5
FREQ2
0
0
0
0
1
1
1
FREQ1
0
0
1
1
0
1
1
FREQ0
0
1
0
1
0/1
0
1
Hsync Freq.
8M/256=31.2K
8M/4/9/5=44.4K
8M/128=62.5K
8M/4/5/5=80K
8M/4/2/11=90.9K
Vsync Freq.
Hsync/512=61.0Hz
Hsync/512=86.8Hz
Hsync/3/5/7/8=74.4Hz
Hsync/1024=78.1Hz
Hsync/1024=88.7Hz
Note
Refer to
Figure 13.7
Disabled Free
Run function
After System
Reset
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