SD1010 Datasheet, PDF (40/46 Pages) List of Unclassifed Manufacturers – Dual-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010
Pixel_h
11 RW 55H[10:8] The x location for reading “Pixel_out” register
56H[7:0]
Pixel_v
11 RW 57H[10:8] The y location for reading “Pixel_out” register
58H[7:0]
Pixle_out
24
R 59H, 5AH, Read out pixel located by “Pixel_h” and “Pixel_v”
5BH
Fc3_start
1 RW 5CH[4] Forces auto calibration to recalculate h back porch
Channel_select
1 RW 5CH[3] Only for single pixel input
0: takes input data from channel 1
1: takes input data from channel 0
Dual_pixel
1 RW 5CH[2] 0: takes input data from one single channel
1: takes input data from both channels
Soft_start
1 RW 5CH[1] Restarts auto calibration without going into reset
ICS_phase_state
1 RW 5CH[0] Forces auto calibration to calculate the image quality
for a particular clock phase when supplied by ics chips
Hsize_by842_en
1 RW 5DH[7] Turn on internal hsize matching by8, 4, 2 when clock
frequency calibration is done by8, 4, 2. Used mainly
for special non-full screen inputs.
Video_mode
1 RW 5DH[6] 0: disable input video mode
1: input is video
Input_yuv
1 RW 5DH[5] 0: input video format is RGB
1: input video format is YUV 4:2:2
Yuv_signed
1 RW 5DH[4] 0: input video YUV format is unsigned
1: input video YUV format is signed
decimation
1 RW 5DH[3] Used when input resolution is higher than output
1: enable special decimation control
0: disable special decimation
Detect_en
2 RW 5DH[2:1] Input data range detection. The results are put in
register 64H and 65H
0: disable detection
1: detect MAX/MIN using R color
2: detect MAX/MIN using G color
3: detect MAX/MIN using B color
Agc_en
1 RW 5DH[0] Automatic gain control enable
Agc_gain_red
8 RW 5EH Gain amount for R color
Agc_gain_green
8 RW 5FH Gain amount for G color
Agc_gain_blue
8 RW 60H Gain amount for B color
Agc_offset_red
8 RW 61H Offset amount for R color
Agc_offset_green
8
RW 62H Offset amount for G color
Agc_offset_blue
8 RW 63H Offset amount for B color
Input_max
8
R 64H Detected maximum input data (please see 5DH)
Input_min
8
R 65H Detected minimum input data (please see 5DH)
ICS_freq_state
1 RW 66H[5] Forces auto calibration to calculate the hsize value for a
particular clock frequency when supplied by ics chips
ICS_hsize_valid
1 RW 66H[4] Indicates when hsize value is ready for cpu to read in
ics mode. Can be clear by cpu
ICS_iq_valid
1 RW 66H[3] Indicates when image quality is ready for cpu to read in
ics mode. Can be clear by cpu
IQ_valid
1 RW 66H[2] Indicates when image quality is ready for cpu to read in
Regular non-ics mode. Can be clear by cpu
Divisor_valid
1 RW 66H[1] Indicates when auto clock frequency calibration is done
and frequency value is ready for cpu to read. Can be
clear by cpu
November, 1999
SmartASIC Confidential
40
Revision B