SD1010 Datasheet, PDF (12/46 Pages) List of Unclassifed Manufacturers – Dual-Interface XGA TFT LCD Display Controller

SmartASIC, Inc.
SD1010
B_OUT5_E
89
O Output Color Blue Even Pixel (left pixel)
B_OUT6_E
90
O Output Color Blue Even Pixel (left pixel)
B_OUT7_E
93
O Output Color Blue Even Pixel (left pixel)
B_OUT0_O
95
O Output Color Blue Odd Pixel (right pixel)
B_OUT1_O
96
O Output Color Blue Odd Pixel (right pixel)
B_OUT2_O
97
O Output Color Blue Odd Pixel (right pixel)
B_OUT3_O
98
O Output Color Blue Odd Pixel (right pixel)
B_OUT4_O
100
O Output Color Blue Odd Pixel (right pixel)
B_OUT5_O
101
O Output Color Blue Odd Pixel (right pixel)
B_OUT6_O
102
O Output Color Blue Odd Pixel (right pixel)
B_OUT7_O
103
O Output Color Blue Odd Pixel (right pixel)
HSYNC_O
31
O Output HSYNC (the polarity is programmable
through CPU, default is active low)
VSYNC_O
32
O Output VSYNC (the polarity is programmable
through CPU, default is active low)
DCLK_OUT
33
O Output Clock to Control Panel (the polarity is
programmable through CPU)
DE_OUT
34
O Output Display Enable for Panel (the polarity is
programmable through CPU, default is active HIGH)
VCLK01
FCLK0
VCLK00
26
I Input Clock 1
27
O Input PLL Feedback Clock
28
I Input Clock 0
FCLK1
VCLK1
29
O Output PLL Feedback Clock
30
I Output PLL Output Clock
ROM_SCL
ROM_SDA
10
O SCL in I²C for EEPROM interface
11
I/O SDA in I²C for EEPROM interface
CPU_SCL
CPU_SDA
13
I SCL in I²C for CPU interface
14
I/O SDA in I²C for CPU interface
PWM_CTL
15
O PWM control signal (Detail description in PWM
Operation Section)
CLK_1M
16
I Free Running Clock (default: 1MHz)
CLK_1M_O
18
O Feedback of free Running Clock
RESET_B
19
I System Reset ( active LOW)
HSYNC_X
41
O Default HSYNC generated by ASIC (active LOW)
VSYNC_X
42
O Default VSYNC generated by ASIC (active LOW)
R_OSD
G_OSD
B_OSD
EN_OSD
20
I OSD Color Red
21
I OSD Color Green
22
I OSD Color Blue
23
I OSD Mixer Enable
=0, No OSD output
=1,R_OUT[7:0]= {R_OSD repeat 8 times}
G_OUT[7:0]= {G_OSD repeat 8 times }
B_OUT[7:0]= {B_OSD repeat 8 times }
November, 1999
SmartASIC Confidential
12
Revision B